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5-28 Intel® PXA255 Processor Developer’s Manual
DMA Controller
When the external device has data to transfer, it makes a DMA request in the standard way. The
DMAC wakes up and reads four words from the device’s I_DESC_OFFS address (the DMAC only
transfers four words because the first descriptor has an 8-byte count.). The four words from the
external device are written in the DSADR, DTADR, and DCMD fields of the next descriptor. The
DMAC then steps into the next (dynamically modified) descriptor and, using the I_DATA_OFFS
address on the external device, starts the transfer that the external device requested. When the
transfer is finished, the DMAC steps back into the first descriptor and the process is repeated.
This example lends itself to any number of variations. For example, a DMA channel that is
programmed in this way can be used to transfer messages from a network device directly into client
buffers. Each block of data would be preceded by its final destination address and a count.
5.5 DMA Controller Register Summary
This section describes the DMAC Registers. Refer to Table 5-13.
Table 5-13. DMA Controller Register Summary (Sheet 1 of 5)
Address Name Description
0x4000_0000 DCSR0 DMA Control / Status Register for Channel 0
0x4000_0004 DCSR1 DMA Control / Status Register for Channel 1
0x4000_0008 DCSR2 DMA Control / Status Register for Channel 2
0x4000_000C DCSR3 DMA Control / Status Register for Channel 3
0x4000_0010 DCSR4 DMA Control / Status Register for Channel 4
0x4000_0014 DCSR5 DMA Control / Status Register for Channel 5
0x4000_0018 DCSR6 DMA Control / Status Register for Channel 6
0x4000_001C DCSR7 DMA Control / Status Register for Channel 7
0x4000_0020 DCSR8 DMA Control / Status Register for Channel 8
0x4000_0024 DCSR9 DMA Control / Status Register for Channel 9
0x4000_0028 DCSR10 DMA Control / Status Register for Channel 10
0x4000_002C DCSR11 DMA Control / Status Register for Channel 11
0x4000_0030 DCSR12 DMA Control / Status Register for Channel 12
0x4000_0034 DCSR13 DMA Control / Status Register for Channel 13
0x4000_0038 DCSR14 DMA Control / Status Register for Channel 14
0x4000_003C DCSR15 DMA Control / Status Register for Channel 15
0x4000_00F0 DINT DMA Interrupt Register
0x4000_0100 DRCMR0
Request to Channel Map Register for DREQ 0
(companion chip request 0)
0x4000_0104 DRCMR1
Request to Channel Map Register for DREQ 1
(companion chip request 1)
0x4000_0108 DRCMR2
Request to Channel Map Register for I2S receive
Request
0x4000_010C DRCMR3
Request to Channel Map Register for I2S transmit
Request