Filter
Top Products
6-68 Intel® PXA255 Processor Developer’s Manual
Memory Controller
The interface waits the smallest possible amount of time (x_ASST_WAIT) before it checks the
value of the nPWAIT signal. If the nPWAIT signal is asserted (active low), the interface continues
to wait (for a variable number of wait states) until nPWAIT is deasserted. When the nPWAIT signal
is deasserted, the command continues to be asserted for a fixed amount of time (x_ASST_HOLD).
6.9 Companion Chip Interface
The processor can be connected to a companion chip in two different ways:
• Alternate Bus Master Mode
• Variable Latency I/O (See Section 6.7.5)
The connection methods are illustrated in Figure 6-31 and Figure 6-32.
Figure 6-30. 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device
Low Byte High Byte
IOx_ASST_HOLD
IOx_ASST_WAIT + wait states
IOx_ASST_HOLD
IOx_ASST_WAIT + wait states
IOx_HOLD
IOx_SET
IOx_HOLD
IOx_SET
0ns 100ns 200ns 300ns
MEMCLK
MA[25:1],nPREG,PSKTSEL
MA[0]
nPCE2
nPCE1
nPIOW,nPIOR
RDnWR
nIOIS16
nPWAIT
read_data
write_data