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Intel® PXA255 Processor Developer’s Manual 16-17
Network SSP Serial Port
16.4.5 FIFO Operation
Two separate and independent FIFOs are present for transmit (to peripheral) and receive (from
peripheral) serial data. FIFOs are filled or emptied by programmed I/O or DMA bursts.
16.4.5.1 Using Programmed I/O Data Transfers
The PXA255 processor can perform FIFO filling and emptying in response to an interrupt from the
FIFO logic. Each FIFO has a programmable trigger threshold at which an interrupt is triggered.
When the number of entries in the receive FIFO exceeds the value in SSCR1[RFT], an interrupt is
generated (if enabled). This interrupt signals the CPU to empty the receive FIFO. When the
number of entries in the transmit FIFO is less than or equal to the value of (SSCR1[TFT] + 1), an
interrupt is generated (if enabled). This interrupt signals the CPU to refill the transmit FIFO.
Reading the SSP Status Register (see Section 16.5.3) shows whether the FIFO is full, empty or
how many samples it contains.
16.4.5.2 Using DMA Data Transfers
The DMA controller can be programmed to transfer data to and from the SSP FIFOs. To prevent
overruns of the transmit FIFO or underruns of the receive FIFO when using the DMA, take care
when setting the transmit and receive trigger thresholds.
The programming model for using the DMA is as:
• Program the total number of transmit and receive byte lengths, burst sizes, and peripheral
width. Program DCMD[WIDTH] to 0b01 for SSP formats of 8 bits or less; to 0b10 for SSP
formats of 9 to 16 bits; to 0b11 for SSP formats of more than 16 bits. When DCMD[WIDTH]
is 0b01 (1 byte), then the DMA burst size must be configured for 8 or 16 bytes per burst.
• Set the preferred values in the SSP control registers.
• Set the SSE bit in the SSP Control Register 0 to enable the SSP (see Section 16.5.1).
• Set the run bits in the DMA Command Register.
• Wait for both the DMA transmit and receive interrupt requests.
• If the transmit/receive byte length is not an even multiple of the transfer burst size, a trailing-
byte condition may occur as described within Section 16.4.2.
• In full-duplex formats where the SSP always receives the same number of data samples as it
transmits, the DMA channel must be set up to transmit and receive the same number of bytes.
16.4.6 Baud-Rate Generation
When the SSP is configured as the master of the SSPSCLK (as determined by
SSCR1[SCLKDIR]), the baud rate (or serial bit-rate clock SSPSCLK) is generated internally by
dividing the 3.6864 MHz clock by a programmable divider (SSCR0[SCR]).
This generates baud rates up to a maximum of 3.68 Mbits per second. When driven by an external
clock, SSPSCLK can be driven up to 13 MHz, generating baud rates up to 13 Mbits per second. At
these fast baud rates, using polled/interrupt mode is insufficient to keep the FIFO filled. You must
use DMA mode.