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12-40 Intel® PXA255 Processor Developer’s Manual
USB Device Controller
12.6.11.3 Endpoint 2 Interrupt Request (IR2)
The interrupt request bit is set if the IM2 bit in the UDC interrupt control register is cleared and the
OUT packet ready bit (RPC) in the UDC endpoint 2 control/status register is set. The IR2 bit is
cleared by writing a 1 to it.
12.6.11.4 Endpoint 3 Interrupt Request (IR3)
The interrupt request bit is set if the IM3 bit in the UDC interrupt control register is cleared and the
IN packet complete (TPC) or Transmit Underrun (TUR) in UDC endpoint 3 control/status register
is set. The IR3 bit is cleared by writing a 1 to it
12.6.11.5 Endpoint 4 Interrupt Request (IR4)
The interrupt request bit is set if the IM4 bit in the UDC interrupt control register is cleared and the
OUT packet ready (RPC) or receiver overflow (ROF) in the UDC endpoint 4 control/status register
or the Isochronous Error Endpoint 4 (IPE4) in the UFNHR are set. The IR4 bit is cleared by writing
a 1 to it.
12.6.11.6 Endpoint 5 Interrupt Request (IR5)
The interrupt request bit is set if the IM5 bit in the UDC interrupt control register is cleared and the
IN packet complete (TPC) in UDC endpoint 5 control/status register is set. The IR5 bit is cleared
by writing a 1 to it.
12.6.11.7 Endpoint 6 Interrupt Request (IR6)
The interrupt request bit gets set if the IM6 bit in the UDC interrupt control register is cleared and
the IN packet complete (TPC) in UDC endpoint 6 control/status register gets set. The IR6 bit is
cleared by writing a one to it.
12.6.11.8 Endpoint 7 Interrupt Request (IR7)
The interrupt request bit is set if the IM7 bit in the UDC interrupt control register is cleared and the
OUT packet ready bit (RPC) in the UDC endpoint 7 control/status register is set. The IR7 bit is
cleared by writing a 1 to it.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.