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Intel® PXA255 Processor Developer’s Manual 6-71
Memory Controller
7. The Memory Controller performs an SDRAM refresh if SDRAM clocks and clock enable are
turned on.
8. The Memory Controller sends an MRS command to the SDRAMs if the MDCNFG:SA1111x
bit is enabled. This changes the SDRAM burst length back to four.
If the refresh counter for the processor requested a refresh cycle during the alternate master’s
tenure, a refresh cycle runs first, followed by any other bus transactions that stalled during that
period.
To enable alternate bus master, the set up the signals by writing the following registers:
• Write the GPIO Pin Direction register GPDR0 to set bit 13 (make GPIO[13] an output) and
clear bit 14 (make GPIO[14] an input)
• Write the GPIO Alternate Function register GAFR0_L to set bits 27 and 26 to 0b11 (enable the
MBGNT alternate function 3) and set bits 29 and 28 to 0b01 (enable the MBREQ alternate
function 1).
6.9.1.1 GPIO Reset
During GPIO reset, the GPIOs, including MBREQ and MBGNT, are set to their reset state. The
MBREQ and MBGNT pins become general purpose inputs. The system must have external put-
downs on these pins to prevent the pins from floating.
If a transaction is in progress when GPIO reset is asserted, the alternate master loses ownership of
the bus. The alternate master must immediately give up the bus when MBGNT is deasserted.
Because the memory controller is not reset, an SDRAM refresh can occur immediately after the
GPIO reset assertion.
6.9.1.2 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Disabled
If an nVDD_FAULT or nBATT_FAULT occurs, the processor places the GPIOs into their sleep
states. MBGNT must be programmed to go low during sleep.
The memory controller prevents the processor from entering sleep until all outstanding transactions
have completed. This includes waiting for the MBREQ signal from the alternate master to deassert.
For best sleep performance, the alternate master must immediately give up the bus when MBGNT
is deasserted. If necessary, the alternate master can hold the bus until its transaction is completed.
After the memory controller has completed all outstanding transactions, it places SDRAM into
self-refresh and allows the processor to complete the sleep entry sequence.
Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is
asserted.
6.9.1.3 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Enabled
If an nVDD_FAULT or nBATT_FAULT occurs with PMCR[IDAE] enabled, the processor causes
an Imprecise Data Abort Exception. This allows the processor to do any required actions before
sleep entry. Sleep entry with PMCR[IDAE] enabled is similar to normal sleep entry. The processor
places the GPIOs into their sleep states. MBGNT must be programmed to go low during sleep.
The memory controller prevents the processor from entering sleep until all outstanding transactions
have completed. This includes waiting for the MBREQ signal from the alternate master to deassert.
For best sleep performance, the alternate master must immediately give up the bus when MBGNT