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Intel® PXA255 Processor Developer’s Manual 8-5
Synchronous Serial Port Controller
Figure 8-2 shows one of the four configurations for the Motorola SPI frame format for single and
back-to-back frame transmissions.
8.4.1.3 Microwire Format Details
Microwire format is similar to SPI, but it uses half-duplex transmissions with master-slave
message passing rather than full-duplex. In idle state or when the SSP is disabled, SSPSCLK is
low, SSPSFRM is high, and SSPTXD is low.
Each Microwire transmission begins with SSPSFRM assertion (low), followed by an 8 or 16-bit
command word sent from controller to peripheral on SSPTXD. The command word data size is
selected by the Microwire Transmit Data Size (MWDS) bit in SSP Control Register 1. SSPRXD is
controlled by the peripheral and remains tristated. SSPSCLK goes high midway through the
command’s most significant bit and continues to toggle at the bit rate.
One bit-period after the last command bit, the peripheral must return the serial data requested, most
significant bit first, on SSPRXD. Data transitions on SSPSCLK’s falling edge and is sampled on
the rising edge. SSPSCLK’s last falling edge coincides with the end of the last data bit on SSPRXD
and it remains low if it is the only or last word of the transfer. SSPSFRM deasserts high one-half
clock period later.
The start and end of a series of back-to-back transfers are similar to those of a single transfer.
However, SSPSFRM remains asserted (low) throughout the transfer. The end of a data word on
SSPRXD is immediately followed by the start of the next command byte on SSPTXD.
Figure 8-2. Motorola SPI* Frame Format
SSPSCLK
...
SSPSFRM
...
SSPTXD Bit<N>
Bit<N-
1>
... Bit<1> Bit<0>
SSPRXD Bit<N>
Bit<N-
1>
... Bit<1> Bit<0>
MSB 4 to 16 Bits LSB
Single Transfer
SSPSCLK
... ...
SSPSFRM
... ...
SSPTX /RX Bit<0> Bit<N>
Bit<N-
1>
... Bit<1> Bit<0> Bit<N>
Bit<N-
1>
... Bit<1> Bit<0>
Continuous Transfers
Note: SSPSCLK’s phase and polarity can be configured for four modes. This example shows one of those modes.