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3-18 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
7. The CPU clock stops and power is removed from the Core.
8. PWR_EN is deasserted.
When the Power Manger get the indication from the Memory Controller that it has finished its
outstanding transactions and has put the SDRAM into self-refresh, there are eight core clock cycles
before the GPIOs latch the PGSR values and four core clock cycles after that, nRESET_OUT
asserts low.
In some systems the Imprecise Data Abort latency lasts longer than the residual charge in the failed
power supply can sustain operation. This normally only occurs when the processor is in a Power
Mode or Sequence that requires that the processor exit before Sleep Mode starts. Frequency
Change Sequence is an example of such a Power Sequence. In these Power Modes and Sequences,
the IDAE bit must not be set. This allows the processor to enters Sleep Mode immediately but any
critical states in the processor are lost.
If the IDAE bit is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the Sleep
Sequence begins at Step 4.
3.4.9.4 Behavior in Sleep Mode
In Sleep Mode, all processor and peripheral clocks are disabled, except the RTC. The processor
does not recognize interrupts or external pin transitions except valid wake-up signals, Reset
signals, and the nBATT_FAULT signal.
If the nBATT_FAULT signal is asserted while in Sleep Mode, GPIO[1:0] are set as the only valid
wake-up signals.
The Power Manager watches for wake up events programmed by the CPU before Sleep Mode
starts or set by the Power Manager it detects a fault condition. In order to detect a rising-edge or
falling-edge on a GPIO pin, the rising- or falling-edge must be held for more than one full
32.768 kHz clock cycle. The Power Manager takes three 32.768 kHz clock cycles to acknowledge
the GPIO edge and begin the wake up sequence.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” on page 2-9 for the
PXA255 processor pin states during sleep mode reset and other resets.
3.4.9.5 Exiting Sleep Mode
Sleep Mode exits when Hardware Reset is asserted. Hardware Reset’s entry and exit sequences
take precedence over Sleep Mode.
Note: If Hardware Reset is asserted during Sleep Mode, the DRAM contents are lost because all states,
including Memory Controller configuration and information about the previous Sleep Mode, are
reset.
Normally, Sleep Mode exits in the following sequence. Any time the nBATT_FAULT pin is
asserted, the processor returns to Sleep Mode. The nVDD_FAULT pin is ignored until the external
power supply stabilization timer expires.
1. A pre-programmed wake up event from an enabled GPIO or RTC source occurs. If the
nBATT_FAULT pin is asserted, the wake up source is ignored.