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10-16 Intel® PXA255 Processor Developer’s Manual
UARTs
5TDRQ
Transmit Data Request: Indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to the processor
when the transmit data request interrupt enable is set high and generates the DMA request
to the DMA controller if DMA requests and FIFO mode are enabled. The TDRQ bit is set
when a character is transferred from the Transmit Holding register into the Transmit Shift
register. The bit is cleared with the loading of the Transmit Holding Register. In FIFO mode,
TDRQ is set to 1 when half of the characters in the FIFO have been loaded into the Shift
register or the RESETTF bit in FCR has been set. It is cleared when the FIFO has more
than half data. If more than 64 characters are loaded into the FIFO, the excess characters
are lost.
0 – There is data in Holding register or FIFO waiting to be shifted out
1 – Transmit FIFO has half or less than half data
4BI
Break Interrupt: BI is set when the received data input is held low for longer than a full word
transmission time (that is, the total time of Start bit + data bits + parity bit + stop bits). The
Break indicator is reset when the processor reads the LSR. In FIFO mode, only one
character equal to 0x00, is loaded into the FIFO regardless of the length of the break
condition. BI shows the break condition for the character at the front of the FIFO, not the
most recently received character.
0 – No break signal has been received
1 – Break signal received
3FE
Framing Error: FE indicates that the received character did not have a valid stop bit. FE is
set when the bit following the last data bit or parity bit is detected to be 0. If the LCR had
been set for two stop bit mode, the receiver does not check for a valid second stop bit. The
FE indicator is reset when the processor reads the LSR. The UART will resynchronize after
a framing error. To do this it assumes that the framing error was due to the next start bit, so
it samples this “start” bit twice and then reads in the “data”. In FIFO mode, FE shows a
framing error for the character at the front of the FIFO, not for the most recently received
character.
0 – No Framing error
1 – Invalid stop bit has been detected
Table 10-13. LSR Bit Definitions (Sheet 2 of 3)
Base+0x14 Line Status Register UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
TEMT
TDRQ
BI
FE
PE
OE
DR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Bits Name Description