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Intel® PXA255 Processor Developer’s Manual 15-11
MultiMediaCard Controller
If the DMA is used, it must be programmed to do 1-byte reads of 32-byte bursts. The last read can
be less than a 32-byte burst. Some examples are:
• Receive 96 bytes of data:
Read 32 bytes three times.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts.
• Receive 98 bytes of data:
Read 32 bytes three times, then read two more bytes.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of two
more bytes and 8-, 16-, or 32- byte bursts.
• Receive 105 bytes:
Read 32 bytes three times, then read nine more bytes.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of nine
or more bytes and 16- or 32-byte bursts.
15.2.8.3 Transmit Data FIFO, MMC_TXFIFO
The two transmit data FIFOs are written only by the software and are writable on a single byte
basis. They are dual FIFOs, where each FIFO is 32 entries of one byte data. Access to the FIFOs is
controlled by the controller and depends on the status of the FIFOs.
Both FIFOs and their controls are cleared to a starting state after a system reset and at the
beginning of all command sequences.
The FIFOs swap between the software and MMC bus. At any time, while the software has write
access to one of the FIFOs, the MMC bus has read access to the other FIFO.
For purposes of an example, the FIFOs are called TXFIFO1 and TXFIFO2. After a reset or at the
beginning of a command sequence, both FIFOs are empty and the software has write access to
TXFIFO1 and the MMC has read access to TXFIFO2. When TXFIFO1 becomes full and
TXFIFO2 is empty, the FIFOs swap and the software has write access to TXFIFO2 and the MMC
has read access to TXFIFO1. When TXFIFO2 becomes full and TXFIFO1 is empty, the FIFOs
swap and the software has write access to TXFIFO1 and the MMC has read access to TXFIFO2.
This swapping process continues through out the data transfer and is transparent to both the
software and the MMC controller.
If at any time both FIFOs become empty and the data transmission is not complete, the controller
turns the MMCLK off to prevent any underruns. When the clock is off, data transmission to the
card stops until the clock is turned back on. When the transmit FIFO is no longer empty, the MMC
controller automatically restarts the clock.
If the software does not fill the FIFO to which it is connected, the
MMC_PRTBUF[BUF_PART_FULL] bit must be set to a 1. This enables the FIFOs to swap
without filling the FIFO.
The empty status of the FIFO that the software is connected to is registered in the
MMC_STAT[XMIT_FIFO_EMPTY] bit.
The transmit FIFO is writable on byte boundaries and the FIFO write request is only asserted once
per FIFO access (once per 32 entries available). Therefore, 32 bytes must be written for each
request, except for the last write which may be less than 32 bytes.