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Intel® PXA255 Processor Developer’s Manual 9-19
I
2
C Bus Interface Unit
5. When an IDBR Receive Full interrupt occurs.
Read ISR: IDBR Receive Full (1), ACK/NAK (0), R/nW bit (0)
6. Read IDBR to get the received byte.
7. Write a 1 to the ISR[IRF] bit to clear interrupt.
8. Return from interrupt.
9. Repeat steps 4 to 8 for n-1 times. Once the IDBR is full, the I
2
C unit will keep SCL low until
the data is read.
10. Set ICR[TB] bit to release I
2
C bus and allow next transfer.
11. When a Slave Stop Detected interrupt occurs.
Read ISR: Unit busy (0), Slave STOP Detected (1)
12. Write a 1 to the ISR[SSD] bit to clear interrupt.
9.6 Master Programming Examples
9.6.1 Initialize Unit
1. Set the slave address in the ISAR.
2. Enable desired interrupts in the ICR. Do not enable Arbitration Loss Detected interrupt
3. Set the ICR[IUE] and ICR[SCLE] bits to enable the I
2
C unit and SCL.
9.6.2 Write 1 Byte as a Master
1. Load target slave address and R/nW bit in the IDBR. R/nW must be 0 for a write.
2. Initiate the write.
Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
3. When an IDBR Transmit Empty interrupt occurs.
Read ISR: IDBR Transmit Empty (1), Unit Busy (1), R/nW bit (0)
4. Write a 1 to the ISR[ITE] bit to clear interrupt.
5. Write a 1 to the ISR[ALD] bit if set.
If the master loses arbitration, it performs an address retry when the bus becomes free. The
Arbitration Loss Detected interrupt is disabled to allow the address retry.
6. Load data byte to be transferred in the IDBR.
7. Initiate the write.
Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[TB]
8. When an IDBR Transmit Empty interrupt occurs (unit is sending STOP).
Read ISR: IDBR Transmit Empty (1), Unit busy (x), R/nW bit (0)
9. Write a 1 to the ISR[ITE] bit to clear the interrupt.
10. Clear ICR[STOP] bit.