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Intel® PXA255 Processor Developer’s Manual 15-13
MultiMediaCard Controller
15.3.1 Basic, No Data, Command and Response Sequence
The MMC controller performs the basic MMC or SPI bus transaction. It formats the command
from the command registers and generates and appends the 7-bit CRC if applicable. It then serially
translates this to the MMCMD bus, collects the response data, and validates the response CRC. It
also checks for response time-outs and card busy if applicable. The response data is in the
MMC_RES FIFO and the status of the transaction is in the status register, MMC_STAT.
The protocol of events for the software is:
1. Stop the clock
2. Write 0x6f to the MMC_I_MASK register and wait for and verify the
MMC_I_REG[CLK_IS_OFF] interrupt
3. Write to these registers, as necessary:
— MMC_CMD
— MMC_ARGH
— MMC_ARGL
— MMC_CMDAT, this register must be written, even if there is no change to the register
— MMC_CLKRT
— MMC_SPI
— MMC_RESTO
4. Start the clock
5. Write 0x7b to the MMC_I_MASK register and wait for and verify the
MMC_I_REG[END_CMD_RES] interrupt
6. Read the MMC_RES FIFO and MMC_STAT registers
Some cards may become busy as the result of a command. The software may wait for the card to
become not busy by writing the MMC_I_MASK register and waiting for the
MMC_I_REG[PRG_DONE] interrupt or the software can start communication to another card.
The software may not access the same card again until the card is no longer busy. Refer to The
MultiMediaCard System Specification for additional information.
15.3.2 Data Transfer
A data transfer is a command and response sequence with the addition of a data transfer to a card.
Refer to the examples in Section 15.4.
The software must follow the steps as described in Section 15.3.1. In addition, before starting the
clock, the software must write these registers as necessary.
• MMC_RDTO
• MMC_BLKLEN
• MMC_NOB
After the software writes the registers and starts the clock, the software must read the MMC_RES
as described above and read or write the MMC_RXFIFO or MMC_TXFIFO FIFOs.