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15-18 Intel® PXA255 Processor Developer’s Manual
MultiMediaCard Controller
3. MMC_SPI[SPI_CS_ADDRESS] must be set to specify the card that the software wants to
address. A 1 enables CS0 and a 0 enables CS1.
Note: When the card is in SPI mode, the only way to return to MMC mode is by toggling power to the
card.
15.4.4 No Data Command and Response Sequence
For the basic no data transfer, command and response transaction, the software must:
1. Turn the clock off, as described in Section 15.4.1.
2. Write the command index in the MMC_CMD[CMD_INDEX] bits.
3. Write the command argument in the MMC_ARGH and MMC_ARGL registers.
4. Write the MMC_CMDAT register set as:
a. Write 0b00 to MMC_CMDAT[RESPONSE_FORMAT].
b. Clear the MMC_CMDAT[DATA_EN] bit.
c. Clear the MMC_CMDAT[BUSY] bit, unless the card may respond busy.
d. Clear the MMC_CMDAT[INIT] bit.
5. Write MMC_RESTO register with the appropriate value.
6. Write 0x1b in MMC_I_MASK to unmask the MMC_I_REG[END_CMD_RES] interrupt.
7. Start the clock, as described in Section 15.4.1.
The software must not make changes in the set of registers until the end of the command and
response sequence, after the clock is turned on.
After the clock is turned on, the software must wait for the MMC_I_REG[END_CMD_RES]
interrupt, which indicates that the command and response sequence is finished and the response is
in the MMC_RES FIFO.
The software may then read the MMC_STAT register to verify the status of the transaction and then
read MMC_RES FIFO. If a response time-out occurred, the MMC_RES FIFO will not contain any
valid data.
15.4.5 Erase
An erase command is performed as described in Section 15.4.4 with the following additions: the
BUSY_BIT in the MMC_CMDAT register must be set to a 1 after it reads the MMC_RES FIFO.
15.4.6 Single Data Block Write
In a single block write command, the software must stop the clock and set the registers as described
in Section 15.4.4. These registers must be set before the clock is started:
• Set MMC_NOB register to 0x0001.
• Set MMC_BLKLEN to the number of bytes per block.