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Intel® PXA255 Processor Developer’s Manual 13-25
AC’97 Controller Unit
13.8.3.5 PCM-Out Status Register (POSR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
13.8.3.6 PCM_In Status Register (PISR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 13-11. POSR Bit Definitions
Physical Address
4050_0010
POSR Register AC’97 Controller Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — reserved
4FIFOE
FIFO error (FIFOE)
0 = No transmit FIFO errors have occurred
1 = A transmit FIFO error occurred. This bit is set if a transmit FIFO underrun occurs. In
this case, the last valid sample is repetitively sent out and the pointers are not
incremented.This could happen due to:
a. No more valid buffer data available for transmits.
b. Buffer data available but DMA controller has excessive bandwidth requirements.
Bit is cleared by writing a 1 to this bit position.
3:0 — reserved
Table 13-12. PISR Bit Definitions
Physical Address
4050_0014
PISR Register AC’97 Controller Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — reserved
4FIFOE
FIFO error (FIFOE)
0 = No Receive FIFO error has occurred.
1 = A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this
case, the FIFO pointers don't increment, the incoming data from the AC-link is not
written into the FIFO and will be lost. This could happen due to DMA controller having
excessive bandwidth requirements and hence not being able to flush out the receive
FIFO in time.
Bit is cleared by writing a 1 to this bit position.
3:0 — reserved