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Intel® PXA255 Processor Developer’s Manual 10-9
UARTs
Bit 7 of the IER is used to enable DMA requests. The IER also contains the unit enable and NRZ
coding enable control bits. Bits 7 through 4 are used differently from the standard 16550 register
definition.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Note: To ensure that the DMA controller and programmed I/O do not access the same FIFO, software
must not set the DMAE while the TIE or RAVIE bits are set to a 1.
10.4.2.5 Interrupt Identification Register (IIR)
The UART prioritizes interrupts in four levels (see Table 10-8) and records them in the IIR. The
IIR, shown in Table 10-9, stores information that indicates that a prioritized interrupt is pending
and identifies the source of the interrupt.
Table 10-7. IER Bit Definitions
Base+0x04 (DLAB=0) Interrupt Enable Register UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
DMAE
UUE
NRZE
RTOIE
MIE
RLSE
TIE
RAVIE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:8 — reserved
7DMAE
DMA Requests Enable.
0 – DMA requests are disabled
1 – DMA requests are enabled
6UUE
UART Unit Enable.
0 – The unit is disabled
1 – The unit is enabled
5NRZE
NRZ coding Enable. NRZ encoding/decoding is only used in UART mode, not in infrared
mode. If the slow infrared receiver or transmitter is enabled, NRZ coding is disabled.
0 – NRZ coding disabled
1 – NRZ coding enabled
4RTOIE
Character Timeout Indication Interrupt Enable.
0 – Character Timeout Indication interrupt disabled
1 – Character Timeout Indication interrupt enabled
3MIE
Modem Interrupt Enable.
0 – Modem Status interrupt disabled
1 – Modem Status interrupt enabled
2RLSE
Receiver Line Status Interrupt Enable.
0 – Receiver Line Status interrupt disabled
1 – Receiver Line Status interrupt enabled
1TIE
Transmit Data request Interrupt Enable.
0 – Transmit FIFO Data Request interrupt disabled
1 – Transmit FIFO Data Request interrupt enabled
0RAVIE
Receiver Data Available Interrupt Enable.
0 – Receiver Data Available (Trigger level reached) interrupt disabled
1 – Receiver Data Available (Trigger level reached) interrupt enabled