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Intel® PXA255 Processor Developer’s Manual 10-15
UARTs
10.4.2.8 Line Status Register (LSR)
The LSR, shown in Table 10-13, provides data transfer status information to the processor.
In non-FIFO mode, LSR[4:2]: parity error, framing error, and break interrupt, show the error status
of the character that has just been received.
In FIFO mode, LSR[4:2] show the status bits of the character that is currently at the front of the
FIFO.
LSR[4:1] produce a receiver line status interrupt when the corresponding conditions are detected
and the interrupt is enabled. In FIFO mode, the receiver line status interrupt only occurs when the
erroneous character reaches the front of the FIFO. If the erroneous character is not at the front of
the FIFO, a line status interrupt is generated after the other characters are read and the erroneous
character becomes the character at the front of the FIFO.
The LSR must be read before the erroneous character is read. LSR[4:1] bits are set until software
reads the LSR.
See Section 10.4.5 for details on using the DMA to receive data.
This is a read-only register. Ignore reads from reserved bits.
Table 10-13. LSR Bit Definitions (Sheet 1 of 3)
Base+0x14 Line Status Register UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
TEMT
TDRQ
BI
FE
PE
OE
DR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Bits Name Description
31:8 — reserved
7FIFOE
FIFO Error Status: In non-FIFO mode, this bit is 0. In FIFO Mode, FIFOE is set to 1 when
there is at least one parity error, framing error, or break indication for any of the characters
in the FIFO. A processor read to the LSR does not reset this bit. FIFOE is reset when all
erroneous characters have been read from the FIFO. If DMA requests are enabled (IER bit
7 is set to 1) and FIFOE is set to 1, the error interrupt is generated and no receive DMA
request is generated even when the receive FIFO reaches the trigger level. Once the errors
have been cleared by reading the FIFO, DMA requests are re-enabled automatically. If
DMA requests are not enabled (IER bit7 is set to 0), FIFOE set to 1 does not generate an
error interrupt.
0 – No FIFO or no errors in receiver FIFO
1 – At least one character in receiver FIFO has errors
6TEMT
Transmitter Empty: Set when the Transmit Holding Register and the Transmitter Shift
Register are both empty. It is cleared when either the Transmit Holding Register or the
Transmitter Shift Register contains a data character. In FIFO mode, TEMT is set when the
transmitter FIFO and the Transmit Shift Register are both empty.
0 – There is data in the Transmit Shift Register, the Transmit Holding Register, or the FIFO
1 – All the data in the transmitter has been shifted out