Filter
Top Products
Intel® PXA255 Processor Developer’s Manual 6-49
Memory Controller
6.7.3.1 ROM Timing Diagrams and Parameters
Figure 6-17, Figure 6-18, and Figure 6-19 show the timings for burst and non-burst ROMs.
Figure 6-17. 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4,
MSC0[RDN] = 1, MSC0[RRR] = 1)
0 1 2 3 4 5 6 7
"00"
"0000"
tDOH
tDSOH
tCEHtCES
RRR*2+1RDF+1
RDN+1RDF+2 RDN+1RDF+2
tAS
tAS = Address Setup to nCS asserted = 1 clk_mem
tCES = nCS setup to nOE asserted = 0 ns
tCEH = nCS hold from nOE deasserted = 0 ns
tDSOH = MD setup to Address changing = 1.5 clk_mems plus
board routing delays
tDOH = MD hold from Address changing = 0 ns
* MSC0:RDF0 = 4, RDN0 = 1, RRR0 = 1
0ns 50ns 100ns 150ns 200ns 250ns
CLK_MEM
nCS[0]
MA[25:5]
MA[4:2]
MA[1:0]
nADV(nSDCAS)
nOE
nWE
RDnWR
MD[31:0]
DQM[3:0]
nCS[1]