Filter
Top Products
Intel® PXA255 Processor Developer’s Manual 3-15
Clocks and Power Manager
3.4.8.3 Exiting 33-MHz Idle Mode
The 33-MHz idle mode exit procedure is the same as the exit procedure for normal idle mode.
However, because the I and F bits are set in the CPSR, the processor does not immediately jump to
the interrupt vector. Instead processing continues with the instruction following the last executed
instruction before 33-MHz idle mode was entered. If execution occurs from SDRAM, steps 1 and 2
must have been previously loaded into the instruction cache. The steps below are then taken:
1. Perform a frequency change to a supported run mode frequency, greater or equal to 100 MHz.
2. Take the SDRAM out of self refresh.
3. Clear the I and F bits in the CPSR. Execution immediately jumps to the pending interrupt
handler.
3.4.9 Sleep Mode
Sleep Mode offers lower power consumption at the expense of the loss of most of the internal
processor state. In Sleep Mode, the processor goes through an orderly shut-down sequence and
power is removed from the core. The Power Manager watches for a wake-up event and, after it
receives one, re-establishes power and goes through a reset sequence. During Sleep Mode, the RTC
and Power Manager continue to function. Pin states can be controlled throughout Sleep Mode and
external SDRAM is preserved because it is in self-refresh mode.
Because all activity on the processor except the RTC stops when Sleep Mode starts, peripherals
must be disabled to allow an orderly shutdown. When Sleep Mode exits, the processor’s state resets
and processing resumes in a boot-up mode.
3.4.9.1 Sleep Mode External Voltage Regulator Requirements
To implement Sleep Mode in the simplest manner, the External Voltage Regulator, which supplies
power to the processor’s internal elements, must have the following characteristics:
• A power enable input pin that enables the primary supply output connected to VCC and
PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep
walk-up by maintaining power during sleep, the regulator should be software configurable to
ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on
before or simultaneously with VCCN and VCCQ. In this configuration, when PWR_EN is
deasserted, the core regulator must be able to maintain regulation when the load power is as
little as 0.5 mW. Core supply current during sleep will vary with voltage and temperature.
• When core power is enabled during sleep, the power management IC or logic that generates
nVDD_FAULT must assert this signal when any supply including VCC and PLL_VCC falls
below the lower regulation limit during sleep. nVDD_FAULT must not be deasserted until all
supplies are in regulation again since there is no power supply stabilization delay during the
fast sleep walk-up sequence. If nVDD_FAULT is asserted during fast sleep walk-up, then the
processor returns to Sleep Mode.
• When configured to disable the core supply to save power during sleep, the core regulator’s
output must be driven to ground when PWR_EN goes low.
• Higher-voltage outputs connected to VCCQ and VCCN are continuously driven and do not
change when the PWR_EN pin is asserted.