Intel PXA255 Personal Computer User Manual


 
5-4 Intel® PXA255 Processor Developer’s Manual
DMA Controller
If all channels request data transfers, the Sets are prioritized in following order:
Set zero
Set one
Set zero
Set two
Set zero
Set one
Set zero
Set three
The pattern repeats for the next eight channel services. In each set, the channels are given round-
robin priority.
The state machine used to determine the priority of the DMA channels is shown in Table 5-3. Use
this table to determine the exact sequence the DMA controller gives to each channel when not all
channels are running concurrently.
The channels get a round-robin priority in each set. Out of reset, the state machine state is zero. If a
channel in set zero has a pending request, that channel is serviced. If a channel in set one has a
pending request, that channel is serviced and so on. Once a request is serviced, the state machine
Table 5-2. Channel Priority (if all channels are running concurrently)
Set Channels Priority Number of times served
0 0,1,2,3 Highest 4 / 8
1 4,5,6,7 Higher 2 / 8
2 8,9,10,11 Low 1 / 8
3 12,13,14,15 Low 1 / 8
Table 5-3. Channel Priority
State Machine
State
DMA Set Priority within each State Machine State
0 S0 > S1 > S2 > S3
1 S1 > S0 > S3 > S2
2 S0 > S1 > S2 > S3
3 S2 > S3 > S0 > S1
4 S0 > S1 > S2 > S3
5 S1 > S0 > S3 > S2
6 S0 > S1 > S2 > S3
7 S3 > S2 > S1 > S0