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Intel® PXA255 Processor Developer’s Manual 12-41
USB Device Controller
12.6.12 UDC Status/Interrupt Register 1 (USIR1)
12.6.12.1 Endpoint 8 Interrupt Request (IR8)
The interrupt request bit is set if the IM8 bit in the UDC interrupt control register is cleared and the
IN packet complete (TPC) or Transmit Underrun (TUR) in UDC endpoint 8 control/status register
is set. The IR8 bit is cleared by writing a 1 to it.
12.6.12.2 Endpoint 9 Interrupt Request (IR9)
The interrupt request bit is set if the IM9 bit in the UDC interrupt control register is cleared and the
OUT packet ready (RPC) or receiver overflow (ROF) in the UDC endpoint 9 control/status register
or the Isochronous Error Endpoint 9 (IPE9) in the UFNHR are set. The IR9 bit is cleared by writing
a 1 to it.
12.6.12.3 Endpoint 10 Interrupt Request (IR10)
The interrupt request bit is set if the IM10 bit in the UDC interrupt control register is cleared and
the IN packet complete (TPC) or in UDC endpoint 10 control/status register is set. The IR10 bit is
cleared by writing a 1 to it.
Table 12-23. USIR1 Bit Definitions
0x 4060_005C USIR1 USB Device Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
IR15
IR14
IR13
IR12
IR11
IR10
IR9
IR8
xxxxxxxxxxxxxxxxxxxxxxxx00000000
Bits Name Description
31:8 — reserved
7IR15
Interrupt Request Endpoint 15 (read/write 1 to clear)
1 = Endpoint 15 needs service.
6IR14
Interrupt Request Endpoint 14 (read/write 1 to clear)
1 = Endpoint 14 needs service.
5IR13
Interrupt Request Endpoint 13 (read/write 1 to clear)
1 = Endpoint 13 needs service.
4IR12
Interrupt Request Endpoint 12 (read/write 1 to clear)
1 = Endpoint 12 needs service.
3IR11
Interrupt Request Endpoint 11 (read/write 1 to clear)
1 = Endpoint 11 needs service.
2IR10
Interrupt Request Endpoint 10 (read/write 1 to clear)
1 = Endpoint 10 needs service.
1IR9
Interrupt Request Endpoint 9 (read/write 1 to clear)
1 = Endpoint 9needs service.
0IR8
Interrupt Request Endpoint 8 (read/write 1 to clear)
1 = Endpoint 8 needs service.