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3-14 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
• SDRAM is placed in self refresh before entering 33-MHz idle mode, because SDRAM cannot
be refreshed correctly in 33-MHz idle mode. Carefully consider the processor interrupt
behavior when the SDRAM in self refresh. To allow the interrupts to occur while SDRAM is
in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor
from idle mode without jumping to the interrupt handler. When the system’s SDRAM is no
longer in self refresh, the I and F bits can be cleared and the interrupt is handled.
• Because nBATT_FAULT and nVDD_FAULT can cause a data abort interrupt, the function of
these pins in 33-MHz idle mode also needs special consideration. Either the Imprecise Data
Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) must be clear,
(causing the processor to immediately enter sleep mode if either nBATT_FAULT or
nVDD_FAULT are asserted) or take software precautions to avoid starting execution in or
trying to use SDRAM while it is in self refresh.
During 33-Mhz idle mode these system unit modules are functional:
• Real-time clock
• Operating system timer
• Interrupt controller
• General purpose I/O
• Clocks and power manager
• Flash ROM/SRAM
Unlike normal idle mode, in 33-MHz idle mode all other peripheral units cannot be used, including
SDRAM, LCD and DMA controllers.
3.4.8.1 Entering 33-MHz Idle Mode
During idle mode, the processor core clocks stop. Before the clocks stop, all critical applications
must be finished and peripherals turned off. If software is executing from SDRAM, the last three of
the following steps must be loaded into the cache before being performed.
1. Set the I and F bits in the CPSR register to mask all interrupts
2. Place the SDRAM into self refresh mode
3. Perform a frequency change sequence to 33MHz mode. The CCCR value for this mode is
0x13F
4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Section 3.7.2)
3.4.8.2 Behavior in 33-MHz Idle Mode
In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode these features of
the processor all operate normally: the RTC timer, the OS timers including the watchdog timer, and
the GPIO interrupt capabilities.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register
(ICMR).