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Intel® PXA255 Processor Developer’s Manual 7-1
LCD Controller 7
The LCD controller provides an interface from the PXA255 processor to a passive (DSTN) or
active (TFT) flat panel display. Monochrome and several color pixel formats are supported.
7.1 Overview
The processor LCD controller supports single- or dual-panel displays. Encoded pixel data created
by the core is stored in external memory in a frame buffer in 1, 2, 4, 8, or 16-bit increments. The
data is fetched from external memory and loaded into a first-in first-out (FIFO) buffer on a demand
basis, using the LCD controller’s dedicated dual-channel DMA controller (DMAC). One channel is
used for single-panel displays and two are used for dual-panel displays.
Frame buffer data contains encoded pixel values that are used by the LCD controller as pointers to
index a 256-entry x 16-bit-wide palette. For 16 bit per pixel frame buffer entries, the palette RAM
is bypassed. Monochrome palette entries are eight bits wide, and color palette entries are 16 bits
wide. The encoded pixel data determines the number of possible colors within the palette as
follows:
• 1-bit-wide pixels address the top 2 locations of the palette
• 2-bit-wide pixels address the top 4 locations of the palette
• 4-bit-wide pixels address the top 16 locations of the palette
• 8-bit-wide pixels address any of the 256 entries within the palette
• 16-bit-wide pixels bypass the palette
When passive color 16-bit pixel mode is enabled, the color pixel values bypass the palette and are
fed directly to the LCD controller’s Frame Rate Control logic. When active color 16-bit pixel mode
is enabled, the pixel value bypasses the palette and the Frame Rate Control logic and is sent
directly to the LCD controller’s data pins. Optionally, the palette RAM is loaded for each frame by
the LCD controller’s DMAC.
Once the encoded pixel value is used to select a palette entry, the value programmed within the
entry is transferred to the Frame Rate Control logic, which uses the Temporal Modulated Energy
Distribution (TMED) algorithm to produce the pixel data that is sent to the screen. Frame Rate
Control is a technique used to create additional color shades by rapidly turning on and off a pixel
on the LCD screen. This is also known as temporal dithering. The data output from the dither logic
is grouped into the selected format (e.g., 8-bit color, dual panel, 16-bit color., etc.) and placed in a
FIFO buffer before being sent out on the LCD controller’s pins and driven to the display using the
pixel clock.
Depending on the type of panel used, the LCD controller is programmed to use either 4-, 8-, or 16-
pixel data output pins. Single-panel monochrome displays use either four or eight data pins to send
4 or 8 pixels for each pixel clock. Single-panel color displays use eight pins to send 2-2/3 pixels
each pixel clock (8 pins / 3 colors/pixel = 2 2/3 pixels per clock). The LCD controller also supports
dual-panel mode, in which the LCD controller’s data lines are split into two groups, one to drive
the top half and one to drive the bottom half of the screen. For dual-panel displays, the number of
pixel data output pins is doubled, allowing twice as many pixels to be sent each pixel clock to the
two halves of the screen.