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Intel® PXA255 Processor Developer’s Manual 13-31
AC’97 Controller Unit
13.8.3.16 Modem Data Register (MODR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
A 32-bit sample write to this register updates the data into the Modem Transmit FIFO. A read to
this register gets a 32-bit sample from the Modem Receive FIFO.
Table 13-21. MISR Bit Definitions
Physical Address
4050_0118
MISR Register AC’97 Controller Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — reserved
4FIFOE
FIFO error (FIFOE)
0 = No Receive FIFO error has occurred.
1 = A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this
case, the FIFO pointers don't increment, the incoming data from the AC-link is not
written into the FIFO and will be lost. This could happen due to DMA controller having
excessive bandwidth requirements and hence not being able to flush out the Receive
FIFO in time.
Bit is cleared by writing a 1 to this bit position.
3:0 — reserved
Table 13-22. MODR Bit Definitions
Physical Address
4050_0140
MODR Register AC’97 Controller Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MODEM_DAT
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:16 — reserved
15:0 MODEM_DAT Modem data