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xii Intel® PXA255 Processor Developer’s Manual
Contents
15.4.11 Stream Read.....................................................................................................15-21
15.5 MMC Controller Registers .............................................................................................15-22
15.5.1 MMC_STRPCL Register...................................................................................15-22
15.5.2 MMC_Status Register (MMC_STAT) ...............................................................15-23
15.5.3 MMC_CLKRT Register (MMC_CLKRT) ...........................................................15-24
15.5.4 MMC_SPI Register (MMC_SPI).......................................................................15-25
15.5.5 MMC_CMDAT Register (MMC_CMDAT) .........................................................15-26
15.5.6 MMC_RESTO Register (MMC_RESTO)..........................................................15-27
15.5.7 MMC_RDTO Register (MMC_RDTO) ..............................................................15-28
15.5.8 MMC_BLKLEN Register (MMC_BLKLEN) .......................................................15-29
15.5.9 MMC_NOB Register (MMC_NOB)...................................................................15-29
15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)......................................................15-30
15.5.11 MMC_I_MASK Register (MMC_I_MASK) ........................................................15-30
15.5.12 MMC_I_REG Register (MMC_I_REG).............................................................15-31
15.5.13 MMC_CMD Register (MMC_CMD) ..................................................................15-33
15.5.14 MMC_ARGH Register (MMC_ARGH)..............................................................15-35
15.5.15 MMC_ARGL Register (MMC_ARGL) ...............................................................15-35
15.5.16 MMC_RES FIFO...............................................................................................15-36
15.5.17 MMC_RXFIFO FIFO.........................................................................................15-36
15.5.18 MMC_TXFIFO FIFO.........................................................................................15-37
15.6 MultiMediaCard Controller Register Summary..............................................................15-37
16 Network SSP Serial Port ............................................................................................................16-1
16.1 Overview..........................................................................................................................16-1
16.2 Features...........................................................................................................................16-1
16.3 Signal Description............................................................................................................16-2
16.4 Operation.........................................................................................................................16-2
16.4.1 Processor and DMA FIFO Access......................................................................16-2
16.4.2 Trailing Bytes in the Receive FIFO.....................................................................16-3
16.4.3 Data Formats......................................................................................................16-3
16.4.4 Hi-Z on SSPTXD...............................................................................................16-13
16.4.5 FIFO Operation.................................................................................................16-17
16.4.6 Baud-Rate Generation......................................................................................16-17
16.5 Register Descriptions.....................................................................................................16-18
16.5.1 SSP Control Register 0 (SSCR0) .....................................................................16-18
16.5.2 SSP Control Register 1 (SSCR1) .....................................................................16-20
16.5.3 SSP Programmable Serial Protocol Register (SSPSP)....................................16-22
16.5.4 SSP Time Out Register (SSTO) .......................................................................16-24
16.5.5 SSP Interrupt Test Register (SSITR)................................................................16-24
16.5.6 SSP Status Register (SSSR)............................................................................16-25
16.5.7 SSP Data Register (SSDR)..............................................................................16-28
16.6 Network SSP Serial Port Register Summary.................................................................16-29
17 Hardware UART.........................................................................................................................17-1
17.1 Overview..........................................................................................................................17-1
17.2 Features...........................................................................................................................17-1
17.3 Signal Descriptions..........................................................................................................17-3
17.4 Operation.........................................................................................................................17-3
17.4.1 Reset ..................................................................................................................17-4
17.4.2 FIFO Operation...................................................................................................17-4