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3-16 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
3.4.9.2 Preparing for Sleep Mode
Before Sleep Mode starts, software must take the following steps:
1. The Memory Controller must be configured to ensure SDRAM contents are maintained during
Sleep Mode. See Section 6, “Memory Controller” for details.
2. If a graceful shutdown is required for a peripheral, the peripheral must be disabled before
Sleep Mode asserts. This includes monitoring DMA transfers to and from peripherals or
memories to ensure they are completed. All other peripherals need not be disabled, since they
are held in their reset states internally during Sleep Mode.
3. The following Power Manager registers must be set up for proper sleep entry and exit:
— PM GPIO Sleep State registers (PGSR0, PGSR1, PGSR2). To avoid contention on the bus
when the processor attempts to wake up, ensure that the chip selects are not set to 0 during
sleep mode. If a GPIO is used as an input, it must not be allowed to float during sleep
mode. The GPIO can be pulled up or down externally or changed to an output and driven
with the unasserted value.
— PM General Configuration Register Float bits [FS/FP] must be configured appropriately
for the system. The General Configuration Register Float bits must be cleared on wake up.
To avoid contention on the bus when the processor attempts to wake up, ensure that the
chip selects are not set to 0 during sleep mode. The PCFR[OPDE] bit must be cleared to
leave the 3.6864 MHz enabled during sleep if the fast walk-up sleep configuration is
selected by setting the PMFW[FWAKE] bit.
— PMFW configuration register must be set to select between the standard and fast sleep
wakeup configurations. Set PMFW[FWAKE] to 1 to disable the 10 ms power supply
stabilization delay during sleep wakeup if power is maintained during sleep. This
configuration reduces the sleep wakeup time to approximately 650
µs.
4. Before the IDAE bit is set, software must configure an imprecise data abort exception handler
to put the processor into sleep mode when a data abort occurs in response to nVDD_FAULT or
nBATT_FAULT assertion. This abort exception event indicates that the processor is in peril of
losing its main power supply.
5. The following Power Manager registers must be set up to detect wake-up sources and
oscillator activity:
— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2).
— PM Wake-up Enable register (PWER)
— PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edge Detect Enable registers
(PFER and PRER)
— OPDE bit in the Power Manager Configuration Register (PCFR)
— IDAE bit in PMCR
Note: The PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast
sleep wakeup is selected by setting the PMFW[FWAKE] bit.
3.4.9.3 Entering Sleep Mode
Software uses the PWRMODE register to enter sleep mode (See Section 3.7.2).