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Intel® PXA255 Processor Developer’s Manual 13-29
AC’97 Controller Unit
13.8.3.12 Modem-Out Control Register (MOCR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
13.8.3.13 Modem-In Control Register (MICR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Figure 13-10. Mic-in Receive-Only Operation
RxEntry0
RxEntry1
RxEntry2
RxEntry3
RxEntry15
15 0
Processor/DMA
RxFIFO
Read
Mic-in Receive FIFO
MCDR Register
31 0
1516
0x0000
Read
Receive
Data
Table 13-18. MOCR Bit Definitions
Physical Address
4050_0100
MOCR Register AC’97
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:4 — reserved
3FEIE
FIFO Error Interrupt Enable (FEIE)
This bit controls whether the occurrence of a transmit FIFO error will cause an interrupt or
not.
0 = No interrupt will occur even if bit 4 in the MOSR is set
1 = An interrupt will occur if bit 4 in the MOSR is set.
2:0 — reserved