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Intel® PXA255 Processor Developer’s Manual iii
Contents
Contents
1 Introduction...................................................................................................................................1-1
1.1 Intel® XScale™ Microarchitecture Features......................................................................1-1
1.2 System Integration Features..............................................................................................1-1
1.2.1 Memory Controller ................................................................................................1-2
1.2.2 Clocks and Power Controllers...............................................................................1-2
1.2.3 Universal Serial Bus (USB) Client.........................................................................1-2
1.2.4 DMA Controller (DMAC) .......................................................................................1-3
1.2.5 LCD Controller ......................................................................................................1-3
1.2.6 AC97 Controller ....................................................................................................1-3
1.2.7 Inter-IC Sound (I2S) Controller.............................................................................1-3
1.2.8 Multimedia Card (MMC) Controller.......................................................................1-3
1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-3
1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-4
1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4
1.2.12 GPIO.....................................................................................................................1-4
1.2.13 UARTs ..................................................................................................................1-4
1.2.14 Real-Time Clock (RTC).........................................................................................1-5
1.2.15 OS Timers.............................................................................................................1-5
1.2.16 Pulse-Width Modulator (PWM) .............................................................................1-5
1.2.17 Interrupt Control....................................................................................................1-5
1.2.18 Network Synchronous Serial Protocol Port...........................................................1-5
2 System Architecture .....................................................................................................................2-1
2.1 Overview............................................................................................................................2-1
2.2 Intel® XScale™ Microarchitecture Implementation Options..............................................2-2
2.2.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-2
2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3
2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3
2.2.4 Coprocessor 15 Register 0 - ID Register Definition..............................................2-3
2.2.5 Coprocessor 15 Register 1 - P-Bit........................................................................2-4
2.3 I/O Ordering.......................................................................................................................2-5
2.4 Semaphores ......................................................................................................................2-5
2.5 Interrupts............................................................................................................................2-5
2.6 Reset .................................................................................................................................2-6
2.7 Internal Registers...............................................................................................................2-7
2.8 Selecting Peripherals vs. General Purpose I/O .................................................................2-7
2.9 Power on Reset and Boot Operation.................................................................................2-8
2.10 Power Management...........................................................................................................2-8
2.11 Pin List...............................................................................................................................2-8
2.12 Memory Map....................................................................................................................2-18
2.13 System Architecture Register Summary..........................................................................2-21
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Clock Manager Introduction...............................................................................................3-1
3.2 Power Manager Introduction..............................................................................................3-2
3.3 Clock Manager...................................................................................................................3-2