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Intel® PXA255 Processor Developer’s Manual 6-31
Memory Controller
Figure 6-9. SDRAM_write
Figure 6-10. SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions
CLtRCD CLtRCD
row col
01 23
mask0 mask1 mask3mask2
tRP = 2 clks
tRCD = 2 clks
tRAS = 2 clks
CL = 2 clks
0ns 25ns 50ns 75ns
SDCLK
nSDCS
MA[24:0]
nSDRAS
nSDCAS
nWE
DATA
DQM[3:0]
read(0) pre(1) act(1) nop write(1) nop
0 1 1
col bank row col
rd0_0 rd0_1 rd0_2 rd0_3 wd1_0 wd1_1 wd1_2 wd1_3
0000 mask0 mask1 mask2 mask3
DTC=00, CL = 2, tRP = 1 clk, tRCD = 1 clk
mask data bytes
SDCLK[1]
SDCKE[1]
command
nSDCS
nSDRAS
nSDCAS
MA[24:10]
nWE
MD[31:0]
DQM[3:0]
RDnWR