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Intel® PXA255 Processor Developer’s Manual 6-23
Memory Controller
Use the information below to connect the processor to the SDRAM devices. Some of the
addressing combinations may not apply in SA1111 addressing mode. See Table 6-10 for a complete
listing of supported addressing combinations and how to connect the PXA255 processor to the
SA1111.
2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2
2x13x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x13x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 25 9 8 7 6 5 4 3 2
2x13x9x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2 1
2x13x10x32 NOT VALID (too big) NOT VALID (too big)
2x13x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 25 9 8 7 6 5 4 3 2 1
2x13x11x32 NOT VALID (too big) NOT VALID (too big)
2x13x11x16 NOT VALID (too big) NOT VALID (too big)
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 3 of 3)
# Bits
Bank x
Row x
Col x
Data
External Address pins at SDRAM RAS Time
MA<24:10>
External Address pins at SDRAM CAS Time
MA<24:10>
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 1 of 3)
# Bits
Bank x
Row x
Col x
Data
Pin mapping to SDRAM devices for Normal Addressing.
MA[24:10] represent the address signals driven from the processor.
MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
1x11x8x32 BA0 A10A9A8A7A6A5A4A3A2A1A0
1x11x8x16 BA0A10A9A8A7A6A5A4A3A2A1A0
1x11x9x32 BA0A10A9A8A7A6A5A4A3A2A1A0
1x11x9x16 BA0A10A9A8A7A6A5A4A3A2A1A0
1x11x10x32 BA0A10A9A8A7A6A5A4A3A2A1A0
1x11x10x16 BA0A10A9A8A7A6A5A4A3A2A1A0
1x11x11x32 NOT VALID (illegal addressing combination)
1x11x11x16 NOT VALID (illegal addressing combination)
1x12x8x32 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x12x8x16 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x12x9x32 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0