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Intel® PXA255 Processor Developer’s Manual 4-13
System Integration Unit
Table 4-15. GRER0 Bit Definitions
Physical Address
0x40E0_0030
GRER0 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE31
RE30
RE29
RE28
RE27
RE26
RE25
RE24
RE23
RE22
RE21
RE20
RE19
RE18
RE17
RE16
RE15
RE14
RE13
RE12
RE11
RE10
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> RE[x]
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 0 through 31).
0 – Disable rising-edge detect enable.
1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
Table 4-16. GRER1 Bit Definitions
Physical Address
0x40E0_0034
GRER1 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE63
RE62
RE61
RE60
RE59
RE58
RE57
RE56
RE55
RE54
RE53
RE52
RE51
RE50
RE49
RE48
RE47
RE46
RE45
RE44
RE43
RE42
RE41
RE40
RE39
RE38
RE37
RE36
RE35
RE34
RE33
RE32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> RE[x]
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 32 through 63).
0 – Disable rising-edge detect enable.
1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
Table 4-17. GRER2 Bit Definitions
Physical Address
0x40E0_0038
GRER2 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
RE84
RE83
RE82
RE81
RE80
RE79
RE78
RE77
RE76
RE75
RE74
RE73
RE72
RE71
RE70
RE69
RE68
RE67
RE66
RE65
RE64
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:21> — reserved
<20:0> RE[x]
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 64 through 80).
0 – Disable rising-edge detect enable.
1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin