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Intel® PXA255 Processor Developer’s Manual 3-11
Clocks and Power Manager
3.4.6.2 Behavior in Idle Mode
In Idle Mode the CPU clocks are stopped, but the remainder of the processor operates normally.
For example, the LCD controller can continue refreshing the screen with the same frame buffer
data in memory.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register.
3.4.6.3 Exiting Idle Mode
Idle Mode exits when any Reset is asserted. Reset entry and exit sequences take precedence over
Idle Mode. When the Reset exit sequence is completed, the CPU is not in Idle Mode. If the
Watchdog Timer is enabled, software must set the Watchdog Match Registers before it sets Idle
Mode to ensure that another interrupt will bring the processor out of Idle Mode before the
Watchdog Reset is asserted. Use an RTC alarm or another OS timer channel for this purpose.
Any enabled interrupt causes Idle Mode to exit. When ICCR[DIM] is cleared, the Interrupt
Controller Mask register (ICMR) is ignored during Idle Mode. This means that an interrupt does
not have to be unmasked to cause Idle Mode to exit. Idle Mode exits in the following sequence:
1. A valid, enabled Interrupt asserts.
2. The CPU clocks restart and the CPU resumes operation at the state indicated by CCLKCFG
[TURBO].
Idle Mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted. When either pin
is asserted, Idle Mode exits in the following sequence:
1. The nBATT_FAULT or nVDD_FAULT pin is asserted.
2. If the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register
(PMCR) is clear (not recommended), the processor enters Sleep Mode immediately.
3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT assertion is treated as a valid
interrupt to the clocks module and Idle Mode exits using its normal, interrupt-driven sequence.
Software must then shut down the system and enter Sleep Mode. See Section 3.4.9.3,
“Entering Sleep Mode” for more details.
3.4.7 Frequency Change Sequence
The Frequency Change Sequence is used to change the processor clock frequency. During the
Frequency Change Sequence, the CPU, Memory Controller, LCD Controller, and DMA clocks
stop. The other peripheral units continue to function during the Frequency Change Sequence. This
mode is intended to be used to change the frequency from the default condition at initial boot-up. It
may also be used as a power-saving feature used to allow the processor to run at the minimum
required frequency when the software requires major changes in frequency.
3.4.7.1 Preparing for a Frequency Change Sequence
Software must complete the following steps before it initiates the Frequency Change Sequence: