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4-10 Intel® PXA255 Processor Developer’s Manual
System Integration Unit
When a GPIO is configured as an output, the state of the pin can be controlled by writing to either
the GPSR or GPCR. An output pin is set high by writing a one to its corresponding bit within the
GPSR. To clear an output pin, a one is written to the corresponding bit within the GPCR. GPSR
and GPCR are write-only registers. Reads return unpredictable values.
Writing a zero to any of the GPSR or GPCR bits has no effect on the state of the pin. Writing a one
to a GPSR or GPCR bit corresponding to a pin that is configured as an input is effective only after
the pin is configured as an output. Reserved bits (GPSR2[31:17] and GPCR2[31:17]), must be
written with zeros and reads must be ignored.
Table 4-9, Table 4-10, and Table 4-11 show the bit definitions of GPSR0, GPSR1, and GPSR2.
Table 4-12, Table 4-13, and Table 4-14 show the bit definitions of GPCR0, GPCR1, and GPCR2.
Table 4-9. GPSR0 Bit Definitions
Physical Address
0x40E0_0018
GPSR0 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS31
PS30
PS29
PS28
PS27
PS26
PS25
PS24
PS23
PS22
PS21
PS20
PS19
PS18
PS17
PS16
PS15
PS14
PS13
PS12
PS11
PS10
PS9
PS8
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> PS[x]
GPIO Pin ‘x’ Output Pin Set (where x= 0 through 31).
0 – Pin level unaffected.
1 – If pin configured as an output, set pin level high (one).
Table 4-10. GPSR1 Bit Definitions
Physical Address
0x40E0_001C
GPSR1 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS63
PS62
PS61
PS60
PS59
PS58
PS57
PS56
PS55
PS54
PS53
PS52
PS51
PS50
PS49
PS48
PS47
PS46
PS45
PS44
PS43
PS42
PS41
PS40
PS39
PS38
PS37
PS36
PS35
PS34
PS33
PS32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> PS[x]
GPIO Pin ‘x’ Output Pin Set (where x= 32 through 63).
0 – Pin level unaffected.
1 – If pin configured as an output, set pin level high (one).