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7-42 Intel® PXA255 Processor Developer’s Manual
LCD Controller
7.6.9 TMED RGB Seed Register (TRGBR)
TRGBR, shown in Table 7-14 contains the three (red, green, blue) eight-bit seed values used by the
TMED algorithm. This value is added into the modified pixel data value as an offset in creating the
lower boundary for the algorithm. These values are used during the dithering process for passive
(DSTN) displays. The default, recommended setting is 0x00AA5500. This setting provides
superior display results in most cases.
This is a write-only register. Write zeros to reserved bits.
Table 7-14. TRGBR Bit Definitions
Physical Address
0x4400_0040
TMED RGB Seed Register LCD Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBS TGS TRS
Reset
X X X X X X X X 0xAA 0x55 0x00
Bits Name Description
31:24 — reserved
23:16 TBS TME Blue Seed value
15:8 TGS TME Green Seed value
7:0 TRS TME Red Seed Value