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7-30 Intel® PXA255 Processor Developer’s Manual
LCD Controller
In active display mode (LCCR0[PAS] = 1), L_BIAS is the output enable signal. However,
signalling of the API interrupt may still occur. The ACB bit field can be used to count line clock
pulses in active mode. When the programmed number of line clock pulses occurs, an internal
signal is toggled that is used to decrement the 4-bit counter used by the API interrupt logic. Once
this internal signal toggles the programmed number of times, as specified by API, an interrupt is
generated. The user must program API to zero if the API interrupt function is not required in active
mode.
AC Bias Pin Frequency (ACB) — In passive display mode (LCCR0[PAS] = 1), the 8-bit ACB
field specifies the number of line clocks to count between each toggle of the AC bias pin
(L_BIAS). After the LCD controller is enabled, the value in ACB is loaded to an 8-bit down
counter, which begins to decrement using the line clock (L_LCLK). When the counter reaches
zero, it stops, L_BIAS is toggled, and the whole procedure starts again. The number of line clocks
between each bias pin transition ranges from 1 to 256, corresponding to ACB values from 0 to 255.
Thus, the value to program into ACB is the desired number of line clocks minus 1.
AC bias is used by a passive LCD display to periodically reverse the polarity of the power supplied
to the screen in order to eliminate D.C. offset. If the LCD display being controlled has its own
internal means of switching its power supply, set ACB to its maximum value (0xFF) to reduce
power consumption. ACB must be programmed conservatively in a system with bandwidth
problems that result in output FIFO underruns in the LCD Controller. In these cases, the pixel clock
is stalled for passive displays, which can result in more time between line clocks than expected.
See Section 7.3.5 for more information on how output FIFO underruns are handled.
In active display mode, the ACB bit field has no effect on the L_BIAS pin. Because the pixel
clock toggles continuously in active mode, the AC bias pin is used as an output enable signal. It is
asserted automatically by the LCD controller in active mode whenever pixel data is driven out to
the data pins to signal the display when it may latch pixels using the pixel clock. ACB can be used
in active mode to count line clocks and generate API interrupts.
Pixel Clock Divider (PCD) — selects the frequency of the pixel clock (L_CLK). PCD can be any
value from 0 to 255. It generates a range of pixel clock frequencies from LCLK/2 to LCLK/512,
where LCLK is the programmed frequency of the LCD/Memory Controller clock. LCLK can vary
from 100MHz to 166 MHz.
The pixel clock frequency must be adjusted to meet the required screen refresh rate, which depends
on:
• number of pixels for the target display
• number of panels (single or dual)
• display type (monochrome or color)
• number of pixel clock wait states programmed at the beginning and end of each line
• number of line clocks inserted at the beginning and end of each frame
• width of the VSYNC signal in active mode or VSW line clocks inserted in passive mode
• width of the frame clock or HSYNC signal.
All of these factors alter the time duration from one frame transmission to the next. Different
display manufacturers require different frame refresh rates, depending on the physical
characteristics of the display. PCD is used to alter the pixel clock frequency in order to meet these
requirements. The frequency of the pixel clock for a set PCD value or the required PCD value to
yield a target pixel clock frequency can be calculated using the two following equations. If double
pixel clock mode (DPC) is enabled, PCD must be set greater than or equal to 1.