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Intel® PXA255 Processor Developer’s Manual 15-17
MultiMediaCard Controller
15.3.4 SPI Functionality
The MMC controller can address up to two cards in SPI mode using the MMCCS[1:0] chip select
signals. Once the software specifies which chip select to enable in the MMC_SPI register, the
selected signal is driven active low at a falling edge of the MMC clock. The chip select remains
asserted until software clears the chip select enable bit or selects another card.
Note: The clock must be stopped before writing to any registers as described in Section 15.3.1.
In SPI mode, the software has the option of performing a CRC check. The default is no CRC
checking.
The command and data are sent on the MMC bus aligned to every 8 clocks as described in the SPI
section of The MultiMediaCard System Specification.
In a read sequence, the card may return data or a data error token. If a data error token is received,
the controller will stop the transmission and update the status register.
15.4 MultiMediaCard Controller Operation
The software directs all communication between the card and the controller. The operations shown
in the preceding sections are valid for MMC mode only.
15.4.1 Start and Stop Clock
The set of registers is accessed by stopping the clock, writing the registers, and starting the clock.
The software stops the clock, as:
1. Write 0x01 in MMC_STRPCL to stop the MMC clock.
2. Write 0x0f in MMC_I_MASK to mask all interrupts except the MMC_I_REG[CLK_IS_OFF]
interrupt.
3. Wait for the MMC_I_REG[CLK_IS_OFF] interrupt.
To start the clock the software writes 0x02 in MMC_STRPCL.
15.4.2 Initialize
Card initialization sequences must be prefixed with 80 clock cycles. To generate 80 clock cycles
before any command, the software must set the MMC_CMDAT[INIT] bit.
15.4.3 Enabling SPI Mode
To communicate with a card in SPI mode, the software must set the MMC_SPI register as follows:
1. MMC_SPI[SPI_EN] must be set to 1.
2. MMC_SPI[SPI_CS_EN] must be set to 1.