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Intel® PXA26x Processor Family Developer’s Manual xi
Contents
14.3.5 Receive FIFO Errors...........................................................................................14-5
14.3.6 Trailing Bytes ......................................................................................................14-5
14.4 Serial Audio Clocks and Sampling Frequencies..............................................................14-5
14.5 Data Formats...................................................................................................................14-6
14.5.1 FIFO and Memory Format ..................................................................................14-6
14.5.2 I2S and MSB-Justified Serial Audio Formats......................................................14-6
14.6 I
2
S Controller Register Descriptions ................................................................................14-7
14.6.1 Serial Audio Controller Global Control Register (SACR0) ..................................14-8
14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)..............14-10
14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)................14-11
14.6.4 Serial Audio Clock Divider Register (SADIV)....................................................14-13
14.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................14-13
14.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-14
14.6.7 Serial Audio Data Register (SADR) ..................................................................14-14
14.6.8 Controller: Register Memory Map.....................................................................14-15
14.7 Interrupts........................................................................................................................14-16
15 MultiMediaCard Controller..........................................................................................................15-1
15.1 Overview..........................................................................................................................15-1
15.2 MultiMediaCard Controller Functional Description ..........................................................15-4
15.2.1 Signal Description...............................................................................................15-4
15.2.2 MultiMediaCard Controller Reset........................................................................15-5
15.2.3 Card Initialization Sequence...............................................................................15-5
15.2.4 MMC and SPI Modes..........................................................................................15-5
15.2.5 Error Detection....................................................................................................15-7
15.2.6 Interrupts.............................................................................................................15-7
15.2.7 Clock Control ......................................................................................................15-7
15.2.8 Data FIFOs .........................................................................................................15-8
15.3 Card Communication Protocol.......................................................................................15-11
15.3.1 Basic, No Data, Command and Response Sequence......................................15-11
15.3.2 Data Transfer....................................................................................................15-12
15.3.3 Busy Sequence.................................................................................................15-15
15.3.4 SPI Functionality...............................................................................................15-15
15.4 MultiMediaCard Controller Operation ............................................................................15-15
15.4.1 Start and Stop Clock.........................................................................................15-16
15.4.2 Initialize.............................................................................................................15-16
15.4.3 Enabling SPI Mode ...........................................................................................15-16
15.4.4 No Data Command and Response Sequence..................................................15-16
15.4.5 Erase ................................................................................................................15-17
15.4.6 Single Data Block Write ....................................................................................15-17
15.4.7 Single Block Read ............................................................................................15-18
15.4.8 Multiple Block Write ..........................................................................................15-18
15.4.9 Multiple Block Read..........................................................................................15-19
15.4.10 Stream Write.....................................................................................................15-19
15.4.11 Stream Read.....................................................................................................15-20
15.5 MultiMediaCard Controller Register Descriptions..........................................................15-21
15.5.1 MMC_STRPCL Register...................................................................................15-21
15.5.2 MMC_STAT Register........................................................................................15-22
15.5.3 MMC_CLKRT Register .....................................................................................15-23
15.5.4 MMC_SPI Register ...........................................................................................15-24