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Intel® PXA26x Processor Family Developer’s Manual 10-1
Universal Asynchronous Receiver/
Transmitter 10
This chapter describes the three universal asynchronous receiver/transmitter (UART) serial ports
without hardware flow control. Because the Hardware UART is configured differently than the
other three, it is described in Section 17, “Hardware UART”. The serial ports are controlled via
direct memory access (DMA) or programmed I/O. This section describes the full function UART,
Bluetooth UART, and standard UART. These UARTS use the same programming model.
10.1 Feature List
The UARTs share these features:
• Functionally compatible with the 16550
• Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in
the serial data
• Independently controlled transmit, receive, line status, and data set interrupts
• Programmable baud rate generator that allows the internal clock to be divided by 1 to 2
16
–1 to
generate an internal 16X clock
• Modem control pins that allow flow control through software. Each UART has different
modem control capability.
• Fully programmable serial-interface:
— 5-, 6-, 7-, or 8-bit characters
— Even, odd, and no parity detection
— 1, 1.5, or 2 stop bit generation
— Baud rate generation up to 921.6 Kbps
• 64-byte transmit FIFO
• 64-byte receive FIFO
• Complete status reporting capability
• Ability to generate and detect line breaks
• Internal diagnostic capabilities that include:
— Loopback controls for communications link fault isolation
— Break, parity, and framing error simulation
• Fully prioritized interrupt system controls
• Separate DMA requests for transmit and receive data services
• Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA)
standard