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Intel® PXA26x Processor Family Developer’s Manual 5-11
Direct Memory Access Controller
5.1.8 Trailing Bytes
The DMAC normally transfers bytes equal to the transaction size specified by DCMD[SIZE]. As
the descriptor nears the end its data, the number of trailing bytes in the DCMD[LENGTH] field
may be smaller than the transfer size. The DMA can transfer the exact number of trailing bytes if
the DCMD[FLOWSRC] and DCMD[FLOWTRG] bits are both 0 or if it receives a corresponding
request from a peripheral or companion chip.
Trailing bytes must be considered in these cases:
• Memory-to-Memory Moves: The DMA transfers a number bytes equal to the smaller of
DCMD[LENGTH] or DCMD[SIZE].
• Companion-Chip Related Transfers: The companion-chip must assert the request if the DMAC
must handle the trailing bytes. If the request is asserted, the DMA transfers a number of bytes
equal to the smaller of DCMD[LENGTH] or DCMD[SIZE].
• Memory to internal peripheral transfers: Most peripherals send a request for trailing bytes
during memory to internal peripheral transfers. Refer to the appropriate section in this
document for details of a peripheral’s operation. The DMA transfers bytes equal to the smaller
of DCMD[LENGTH] or DCMD[SIZE].
• Internal Peripheral to Memory Transfers: Most peripherals do not send a request for trailing
bytes for on-chip peripheral to memory transfers. Refer to the appropriate section in this
document for details of a peripheral’s operation. If the peripheral sends out a request, the DMA
transfers the number of bytes equal to the smaller of DCMD[LENGTH] or DCMD[SIZE]. If
software must us programmed I/O to handle the trailing bytes, it must follow this sequence of
operation:
1. Writing a 0 to the DCSR[RUN] bit to stop the DMA channel.
2. Wait until the channel to stops.
3. Make reads to the channel’s registers to check the channel’s status.
4. Perform the programmed I/O transfers to the peripheral.
5. Set the DCSR[RUN] bit to a 1 and reset the DMA channel for future data transfers.
5.2 Transferring Data
The internal peripherals are connected to the DMAC via the peripheral bus and use flow-through
data transfers. The DMAC can also transfer data to and from any memory location with memory-
to-memory moves in flow-through transfer mode. External devices, such as companion chips, that
are directly connected to the external data pins must use flow-through data transfers.
Main memory includes any memory that the processor supports, except writes to flash. Writes to
flash are not supported and cause a bus error.
In flow-through transfer mode, data passes through the DMAC before it is latched by the
destination in its buffers/memory. The DMAC can also perform memory-to-memory moves in
flow-through transfer mode.