Filter
Top Products
Intel® PXA26x Processor Family Developer’s Manual 16-29
Network/Audio Synchronous Serial Protocol Serial Ports
16.5.5 SSP Interrupt Test Register (SSITR)
SSITR, shown in Table 16-7 on page 16-29, contains bit fields used for testing purposes only.
Setting bits in this register causes the SSP port controller to generate interrupts and DMA requests
if enabled. This is useful in testing the port’s functionality.
Setting any of these bits also causes the corresponding status bit(s) to be set in the SSP Status
Register (SSSR). The interrupt or service request caused by the setting of one of these bits remains
active until the bit is cleared.
These are read/write registers. Ignore read from reserved bits. Write zeros to reserved bits.
Table 16-6.
SSTO Bit Definitions
Physical Address
Base + 0x28
SSTO
PXA26x processor family Network/Audio
SSP Serial Ports
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved TIMEOUT
Reset
? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Access Name Description
31:24 — — Reserved
23:0 R/W TIMEOUT
TIMEOUT:
Value used to set the time-out interval. When the TIMEOUT value is
cleared, no time-out occurs and SSSR[TINT] is not set.
The time-out interval is given by the equation: Time-out Interval =
(TIMEOUT) / Peripheral Clock Frequency
Table 16-7. SSITR Bit Definitions (Sheet 1 of 2)
Physical Address
Base + 0x0C
SSITR
PXA26x processor family Network/Audio
SSP Serial Ports
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TROR
TRFS
TTFS
Reserved
Reset
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? ? ? ? ?
Bits Access Name Description
31:8 — — Reserved
7R/WTROR
TEST RECEIVE FIFO OVERRUN:
0 – No receive FIFO overrun service request is generated.
1 – Generates a non-maskable Interrupt to the CPU. No DMA request
is generated.