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Intel® PXA26x Processor Family Developer’s Manual 15-13
MultiMediaCard Controller
The MMC controller performs data transactions in all the basic modes: single block, multiple
blocks, and stream modes.
15.3.2.1 Block Data Write
In a single block data write, a block of data is written to a card. In a multiple block write, the
controller performs multiple single block write data transfers on the MMC bus.
After turning the clock on to start the command sequence, the software must program the DMA to
fill the MMC_TXFIFO (write 32 bytes). The software must continue to fill the FIFO until all of the
data has been written to the FIFOs. The software must then wait for the transmission to complete
by waiting for the MMC_I_REG[DATA_TRAN_DONE] interrupt and
MMC_I_REG[PRG_DONE] interrupt. The software can then read the status register,
MMC_STAT, to verify the status of the transaction.
For multiple block writes, the MultiMediaCard System Specification, Version 2.1 specifies that the
card will continue to receive blocks of data until the stop transmission command is received. After
the controller has transmitted the number of bytes specified in the MMC_NOB register, the
controller will stop transmitting data. After the MMC_I_REG[DATA_TRAN_DONE] interrupt is
detected, the software must setup the controller to send the stop transmission command, CMD12.
Consult the MultiMediaCard System Specification, Version 2.1 for a description of the stop
transmission command.
If both transmit FIFOs become empty during data transmission, the MMC controller turns the
clock off. After a FIFO has been written, the controller turns the clock back on.
In a block data write, the following parameters must be specified:
• The data transfer is a write.
• The block length if the block length is different from the previous block data transfer or this is
the first time that the parameter is being specified.
• The number of blocks to be transferred.
15.3.2.2 Block Data Read
In a single block data read, a block of data is read from a card. In a multiple block read, the
controller performs multiple single block read data transfers on the MMC bus.
After turning the clock on to start the command sequence, the software must program the DMA to
empty the MMC_RXFIFO (read 32 bytes). The software will continue the process of emptying the
FIFO until all of the data has been read from the FIFO. The software must then wait for the
transmission to complete by waiting for the MMC_I_REG[DATA_TRAN_DONE] interrupt. The
software can then read the status register, MMC_STAT, to verify the status of the transaction.
For multiple block reads, the MultiMediaCard System Specification, Version 2.1 specifies that the
card will continue to send blocks of data until the stop transmission command is received. After the
controller has received the number of bytes specified in the MMC_NOB register, the controller will
stop receiving data. After the MMC_I_REG[DATA_TRAN_DONE] interrupt is detected, the
software must set up the controller to send the stop transmission command, CMD12. Consult the
MultiMediaCard System Specification, Version 2.1 for a description of the stop transmission
command.
If both receive FIFOs become full during the data transmission, the controller turns the clock off.
Once the software empties the FIFO to which it is connected, the controller turns the clock back on.