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3-26 Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)
The PRER, refer to Table 3-10, determines whether the GPIO pin enabled via the PWER register
causes a sleep-mode wake up on the GPIO pin’s rising edge. When the IDAE bit is zero and a fault
condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PRER is set to 0x0000 0003.
This enables rising edges on GP[1:0] to act as wake up sources. When the IDAE bit is set, fault
conditions on the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PRER is
also set to 0x0000 0003 in hardware, watchdog, and GPIO resets.
Software should enable wake ups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-10. PRER Bit Definitions
0x40F0_0010 PRER Clocks and Power Manager
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RE15
RE14
RE13
RE12
RE11
RE10
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
[31:16] — Reserved
[15:0] REx
SLEEP MODE RISING-EDGE WAKE-UP ENABLE:
0 – Wake up due to GPx rising-edge detect disabled.
1 – Wake up due to GPx rising-edge detect enabled.
Set to 0x 0003 on hardware, watchdog, and GPIO resets.