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Intel® PXA26x Processor Family Developer’s Manual 13-31
AC97 Controller Unit
13.8.3.16 Modem-In Status Register (MISR)
13.8.3.17 Modem Data Register (MODR)
A 32-bit sample write to this register updates the data into the modem transmit FIFO. A read to this
register gets a 32-bit sample from the modem receive FIFO.
Table 13-22. Modem-In Status Register
Physical Address
4050_0118
MISR Register AC97
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FIFOE
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — Reserved
4FIFOE
FIFO ERROR (FIFOE):
0 – No receive FIFO error has occurred.
1 – A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this
case, the FIFO pointers don't increment, the incoming data from the AC-link is not
written into the FIFO and the incoming data is lost. This could happen due to DMA
controller having excessive bandwidth requirements and hence not being able to flush
out the receive FIFO in time.
Bit is cleared by writing a 1 to this bit position.
3:0 — Reserved
Table 13-23. Modem Data Register
Physical Address
4050_0140
MODR Register AC97
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved MODEM_DAT
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:16 — Reserved
15:0 MODEM_DAT Modem data