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Intel® PXA26x Processor Family Developer’s Manual 4-9
System Integration Unit
This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
Whether a pin is an input or an output is controlled by programming the GPIO Pin Direction
registers (GPDR0, GPDR1, GPDR2). The GPDR registers contain one direction control bit for
each of the 90 GPIO pins. For GPIO[85:0], if a direction bit is programmed to a one, the GPIO is
an output. If it is programmed to a zero, it is an input. For GPIO[89:86], if a direction bit is
programmed to a one, the GPIO is an input. If it is programmed to a zero, it is an output. Reserved
bits (GPDR2[31:26]), must be written to zeros and reads to the reserved bits must be ignored.
Note: A reset clears all bits in the GPDR0-2 registers and configures GPIO[85:0] as inputs and
GPIO[89:86] as outputs.
Table 4-6, Table 4-7, and Table 4-8 show the bitmaps of the GPIO Pin Direction registers.
Table 4-4. GPLR1 Bit Definitions
Physical Address
0x40E0_0004
GPLR1 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PL63
PL62
PL61
PL60
PL59
PL58
PL57
PL56
PL55
PL54
PL53
PL52
PL51
PL50
PL49
PL48
PL47
PL46
PL45
PL44
PL43
PL42
PL41
PL40
PL39
PL38
PL37
PL36
PL35
PL34
PL33
PL32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> PL[x]
GPIO Pin Level ‘x’ (where x = 32 to 63).
This read-only field indicates the current value of each GPIO.
0 – Pin state is low
1 – Pin state is high
Table 4-5. GPLR2 Register Bitmap
Physical Address
0x40E0_0008
GPIO Pin Level Register2 (GPLR2) System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PL89
PL88
PL87
PL86
PL85
PL84
PL83
PL82
PL81
PL80
PL79
PL78
PL77
PL76
PL75
PL74
PL73
PL72
PL71
PL70
PL69
PL68
PL67
PL66
PL65
PL64
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:26> — Reserved
<25:0> PL[x]
GPIO Pin Level ‘x’ (where x = 64 to 89).
This read-only field indicates the current value of each GPIO.
0 – Pin state is low
1 – Pin state is high