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7-46 Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
7.6.7.10 Start Of Frame Status (SOF)
SOF status is set after the DMA controller has loaded a new descriptor and that descriptor has the
start of frame interrupt bit set (LDCMDx[SOFINT]=1). When SOF is set, an interrupt request is
made to the interrupt controller if it is unmasked (LCCR0[SFM]=0). In dual-panel mode
(LCCR0[SDS]=1), both DMA channels are enabled, and SOF is set only after both channels’
descriptors have been loaded. SOF remains set until cleared by software.
7.6.7.11 LCD Disable Done Status (LDD)
LDD is set by hardware after the LCD has been disabled and the frame that is active has been sent
to the LCD data pins. When the LCD controller is disabled by setting the LCD disable bit
in
LCCR0, the current frame is completed before the controller is disabled. After the last set of pixels
is clocked out onto the LCD data pins by the pixel clock, the LCD controller is disabled, LDD is
set, and an interrupt request is made to the interrupt controller if it is unmasked (LCCR0[LDM]=0).
LDD remains set until cleared by software.
Performing a quick disable by clearing LCCR0[ENB] does not set LDD.
7.6.8 LCD Controller Interrupt ID Register (LIIDR)
LIIDR is a read-only register (Table 7-13). It contains a copy of the Frame ID Register (FIDR)
from the descriptor currently being processed when a start of frame (SOF), end of frame (EOF),
branch (BS), or bus error (BER) interrupt is signalled. LIIDR is written to only when an unmasked
interrupt of the above type is signalled and there are no other unmasked interrupts in the LCD
controller pending. As such, the register is considered to be sticky and will be overwritten only
when the signalled interrupt is cleared by writing the LCD controller status register. Except for a
bus error, in dual panel mode LIIDR is written only when both channels have reached a given state.
LIIDR is written with the last channel to reach that state. (for example, FIDR of the last channel to
reach SOF would be written in LIIDR if SOF interrupts are enabled). Write reserved bits with zeros
and ignore reads from reserved bits.
7.6.9 TMED RGB Seed Register
This register (Table 7-14) contains the three (red, green, blue) eight-bit seed values used by the
TMED algorithm. This value is added into the modified pixel data value as an offset in creating the
lower boundary for the algorithm. These values are used during the dithering process for passive
Table 7-13. LCD Controller Interrupt ID Register
Physical Address
0x4400_003C
LCD Controller Interrupt ID
Register
LCD Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFRAMEID reserved
Reset
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X X X
Bits Name Description
31:3 IFRAMEID INTERRUPT FRAME ID
2:0 — Reserved