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xx Intel® PXA26x Processor Family Developer’s Manual
Contents
10-6 Divisor Latch High Register – DLH..........................................................................................10-8
10-7 Interrupt Enable Register – IER...............................................................................................10-9
10-8 Interrupt Conditions ...............................................................................................................10-11
10-9 Interrupt Identification Register – IIR.....................................................................................10-11
10-10 Interrupt Identification Register Decode ................................................................................10-12
10-11 FIFO Control Register – FCR ................................................................................................10-13
10-12 Line Control Register – LCR..................................................................................................10-14
10-13 Line Status Register – LSR ...................................................................................................10-16
10-14 Modem Control Register – MCR ...........................................................................................10-18
10-15 Modem Status Register – MSR.............................................................................................10-20
10-16 Scratch Pad Register – SPR .................................................................................................10-21
10-17 Infrared Selection Register – ISR..........................................................................................10-24
10-18 FFUART Register Addresses................................................................................................10-26
10-19 BTUART Register Locations .................................................................................................10-26
10-20 STUART Register Locations .................................................................................................10-27
10-21 Flow Control Registers in BTUART and STUART.................................................................10-27
11-1 FICP Signal Description ..........................................................................................................11-1
11-2 Fast Infrared Communication Port Control Register 0.............................................................11-9
11-3 Fast Infrared Communication Port Control Register 1...........................................................11-11
11-4 Fast Infrared Communication Port Control Register 2...........................................................11-11
11-5 Fast Infrared Communication Port Data Register..................................................................11-13
11-6 Fast Infrared Communication Port Status Register 0 ............................................................11-14
11-7 Fast Infrared Communication Port Status Register 1 ............................................................11-15
11-8 FICP Control, Data, and Status Register Locations ..............................................................11-16
12-1 Endpoint Configuration ............................................................................................................12-2
12-2 USB States..............................................................................................................................12-3
12-3 IN, OUT, and SETUP Token Packet Format ...........................................................................12-6
12-4 SOF Token Packet Format......................................................................................................12-6
12-5 Data Packet Format.................................................................................................................12-6
12-6 Handshake Packet Format ......................................................................................................12-6
12-7 Bulk Transaction Formats........................................................................................................12-7
12-8 Isochronous Transaction Formats...........................................................................................12-7
12-9 Control Transaction Formats...................................................................................................12-8
12-10 Interrupt Transaction Formats .................................................................................................12-8
12-11 Host Device Request Summary ..............................................................................................12-9
12-12 UDC Control Register............................................................................................................12-23
12-13 UDC Endpoint 0 Control Status Register ..............................................................................12-26
12-14 UDC Endpoint x Control Status Register, Where x is 1, 6 or 11 ...........................................12-28
12-15 UDC Endpoint x Control Status Register, Where x is 2, 7, or 12 ..........................................12-30
12-16 UDC Endpoint x Control Status Register, Where x is 3, 8, or 13 ..........................................12-33
12-17 UDC Endpoint x Control Status Register, Where x is 4, 9, or 14 ..........................................12-35
12-18 UDC Endpoint x Control Status Register, Where x is 5, 10, or 15 ........................................12-37
12-19 UDC Interrupt Control Register 0 ..........................................................................................12-38
12-20 UDC Interrupt Control Register 1 ..........................................................................................12-39
12-21 UDC Status / Interrupt Register 0..........................................................................................12-41
12-22 UDC Status / Interrupt Register 1..........................................................................................12-43
12-23 UDC Frame Number High Register.......................................................................................12-44
12-24 UDC Frame Number Low Register........................................................................................12-45
12-25 UDC Byte Count Register x, Where x is 2, 4, 7, 9, 12, or 14.................................................12-46
12-26 UDC Endpoint 0 Data Register..............................................................................................12-47