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2-28 Intel® PXA26x Processor Family Developer’s Manual
System Architecture
0x4060 0600 UDDR6 UDC Endpoint 6 Data Register
0x4060 0680 UDDR7 UDC Endpoint 7 Data Register
0x4060 0700 UDDR8 UDC Endpoint 8 Data Register
0x4060 0900 UDDR9 UDC Endpoint 9 Data Register
0x4060 00C0 UDDR10 UDC Endpoint 10 Data Register
0x4060 0B00 UDDR11 UDC Endpoint 11 Data Register
0x4060 0B80 UDDR12 UDC Endpoint 12 Data Register
0x4060 0C00 UDDR13 UDC Endpoint 13 Data Register
0x4060 0E00 UDDR14 UDC Endpoint 14 Data Register
0x4060 00E0 UDDR15 UDC Endpoint 15 Data Register
0x4060 0050 UICR0 UDC Interrupt Control Register 0
0x4060 0054 UICR1 UDC Interrupt Control Register 1
0x4060 0058 USIR0 UDC Status Interrupt Register 0
0x4060 005C USIR1 UDC Status Interrupt Register 1
Standard
UART
0x4070 0000
0x4070 0000 STRBR Receive Buffer Register (read only)
0x4070 0000 STTHR Transmit Holding Register (write only)
0x4070 0004 STIER Interrupt Enable Register (read/write)
0x4070 0008 STIIR Interrupt ID Register (read only)
0x4070 0008 STFCR FIFO Control Register (write only)
0x4070 000C STLCR Line Control Register (read/write)
0x4070 0010 STMCR Modem Control Register (read/write)
0x4070 0014 STLSR Line Status Register (read only)
0x4070 0018 STMSR reserved
0x4070 001C STSPR Scratch Pad Register (read/write)
0x4070 0020 STISR Infrared Selection Register (read/write)
0x4070 0000 STDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4070 0004 STDLH Divisor Latch High Register (DLAB = 1) (read/write)
ICP 0x4080 0000
0x4080 0000 ICCR0 ICP Control Register 0
0x4080 0004 ICCR1 ICP Control Register 1
0x4080 0008 ICCR2 ICP Control Register 2
0x4080 000C ICDR ICP Data Register
0x4080 0010 — reserved
0x4080 0014 ICSR0 ICP Status Register 0
0x4080 0018 ICSR1 ICP Status Register 1
RTC 0x4090 0000
0x4090 0000 RCNR RTC Count Register
0x4090 0004 RTAR RTC Alarm Register
0x4090 0008 RTSR RTC Status Register
Table 2-8. Register Address Summary (Sheet 8 of 13)
Unit Address Register Symbol Register Description