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18-4 Intel® PXA26x Processor Family Developer’s Manual
Internal Flash
;//--- Configure the processor in synchronous mode
;//--- Can be used with normal K3, ensure bus width check is for correct chip
select
;//--- Read the CCCR to check the memory clock frequency
LDR r3,=CCCR
LDR r4,[r3]
AND r4, r4, #0x1F ;/* First 5 bits = L value */
ldr r1, =0x0 ;/* Default to Asynchronous mode */
cmp r4, #0x1 ;/* Memory Frequency = 100 MHz */
ldreq r1, =0x1
cmp r4, #0x2 ;/* Memory Frequency = 118 MHz (Use 133 MHz settings) */
ldreq r1, =0x2
cmp r4, #0x3 ;/* Memory Frequency = 133 MHz */
ldreq r1, =0x2
cmp r4, #0x4 ;/* Memory Frequency = 150 MHz (Use Asynchronous mode)
*/
ldreq r1, =0x0
cmp r4, #0x5 ;/* Memory Frequency = 166 MHz (Use Asynchronous mode)
*/
ldreq r1, =0x0
;//--- If the clock is set to an invalid value, leave in asynch mode
cmp r1, #0x0
beq EndSynchronousMode
;//--- Enable SDCLK[0] as divide-by-2 (all frequencies)
ldr r3, =MDREFR
ldr r2, [r3]
orr r2, r2, #0x00007000
str r2, [r3]
;//--- Configure synch mode for correct frequency
cmp r1, #0x1
beq SDCLK0_50MHz
;//--- Fill up registers with correct values -- 66 MHz
;//--- Check for 16/32 bit mode
ldr r3, =MSC0
ldr r3, [r3]
and r3, r3, #0x8
cmp r3, #0x8
beq SDCLK0_66MHz_16bit
;//--- Configure for 66 MHz/32 bit operation
ldr r3, =SXCNFG
ldr r4, =0x0000d708
ldr r5, =0x00600060
ldr r6, =0x00030003
ldr r7, =0x60f9
b aligned_address_32
SDCLK0_66MHz_16bit
ldr r3, =SXCNFG
ldr r4, =0x00006b84
ldr r5, =0x0060
ldr r6, =0x0003
ldr r7, =0x60f9
b aligned_address_16