Filter
Top Products
Intel® PXA26x Processor Family Developer’s Manual 15-17
MultiMediaCard Controller
The software must not make changes in the set of registers until the end of the command and
response sequence, after the clock is turned on.
After the clock is turned on, the software must wait for the MMC_I_REG[END_CMD_RES]
interrupt, which indicates that the command and response sequence is finished and the response is
in the MMC_RES FIFO.
The software may then read the MMC_STAT register to verify the status of the transaction and then
read MMC_RES FIFO. If a response time-out occurred, the MMC_RES FIFO will not contain any
valid data.
15.4.5 Erase
An erase command is performed as described in the previous section, Section 15.4.4, “No Data
Command and Response Sequence” with the following additions: The BUSY_BIT in the
MMC_CMDAT register must be set to a 1 after it reads the MMC_RES FIFO.
15.4.6 Single Data Block Write
In a single block write command, the software must stop the clock and set the registers as described
in section Section 15.4.4, “No Data Command and Response Sequence”. The following registers
must be set before the clock is started:
• Set MMC_NOB register to 0x0001.
• Set MMC_BLKLEN to the number of bytes per block.
• Update the MMC_CMDAT register as follows:
— Write 0x01 to MMC_CMDAT[RESPONSE_FORMAT]
— Set the MMC_CMDAT[DATA_EN] bit.
— Set the MMC_CMDAT[WRITE/READ] bit.
— Clear the MMC_CMDAT[STREAM_BLOCK] bit.
— Clear the MMC_CMDAT[BUSY] bit.
— Clear the MMC_CMDAT[INIT] bit.
• Turn the clock on.
After it starts the clock, the software must perform the following steps:
1. Wait for the response as described in section Section 15.4.4, “No Data Command and
Response Sequence”.
2. Write data to the MMC_TXFIFO FIFO and continue until all of the data has been written to
the FIFO.
Note: If a piece of data smaller than 32 bytes is written to the FIFO, the MMC_PRTBUF register must be
set.
3. Set MMC_I_MASK register to 0x1e and wait for MMC_I_REG[DATA_TRAN_DONE]
interrupt.
4. Set MMC_I_MASK to 0x1d.