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Intel® PXA26x Processor Family Developer’s Manual 3-15
Clocks and Power Manager
If hardware or watchdog reset is asserted during the frequency change sequence, the DRAM
contents are lost because all states, including memory controller configuration and information
about the previous frequency change sequence, are reset. If GPIO reset is asserted during the
frequency change sequence, the SDRAM contents are lost during the GPIO reset exit sequence if
the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh interval.
Normally, the frequency change sequence exits in this sequence:
1. The processor’s PLL clock generator is reprogrammed with the desired values (in the CCCR)
and begins to relock to those values.
Note: The frequency change sequence occurs even if the before and after frequencies are the same.
2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification for
details.
3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either run or turbo mode). Interrupts to the CPU are no longer gated.
4. The FCS bit is not automatically cleared. To prevent an accidental return to the frequency
change sequence, software must not immediately clear the FCS bit. The bit must be cleared on
the next required write to the register.
5. Values may be written to the CCCR, but they are ignored until the frequency change sequence
is re-entered.
6. The SDRAM must transition out of self-refresh mode and into its idle state. See Chapter 6,
“Memory Controller” for details on configuring the SDRAM interface.
3.4.9 Sleep Mode
Sleep mode offers lower power consumption at the expense of the loss of most of the internal
processor state. In sleep mode, the processor goes through an orderly shut-down sequence. The
PXA26x processor family supports two sleep mode configurations: one that minimizes power
consumption and one that minimizes sleep exit latency.
To minimize power consumption during sleep, drive the VCC and PLL_VCC supplies to ground
when PWR_EN deasserts. To minimize sleep exit latency:
• VCC and PLL_VCC power supplies must remain enabled during sleep
• Software must disable the power supply stabilization delay during the wake-up sequence
When in sleep mode, the power manager watches for a wake-up event and, after it receives one, re-
establishes power (if needed) and goes through a reset sequence. During sleep mode, the RTC and
power manager continue to function. Pin states can be controlled throughout sleep mode and
external SDRAM is preserved because it is in self-refresh mode.
Because all processor activity (except the RTC) stops when sleep mode starts, peripherals must be
disabled to allow an orderly shutdown. When sleep mode exits, the processor’s state resets and
processing resumes in a boot-up mode.
3.4.9.1 Sleep Mode External Voltage Regulator Requirements
For maximum flexibility with the implementation of sleep mode, the external power supply system
must have these characteristics: