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14-16 Intel® PXA26x Processor Family Developer’s Manual
Inter-Integrated Circuit Sound Controller
14.7 Interrupts
The following SASR0 status bits, if enabled, interrupt the processor:
• Receive FIFO Service DMA Request (RFS)
• Transmit FIFO Service DMA Request (TFS)
• Transmit Under-run (TUR)
• Receive Over-run (ROR).
Note: For further details, see Section 14.6.3, “Serial Audio Controller I2S/MSB-Justified Status Register
(SASR0)”.
Table 14-12. Register Memory Map
Address
(paddr(9:0)
Register name Description
0x4040-0000 SACR0 Global Control Register
0x4040-0004 SACR1 Serial Audio I
2
S/MSB-Justified Control Register
0x4040-0008 — Reserved
0x4040-000C SASR0 Serial Audio I
2
S/MSB-Justified Interface and FIFO Status Register
0x4040-0014 SAIMR Serial Audio Interrupt Mask Register
0x4040-0018 SAICR Serial Audio Interrupt Clear Register
0x4040-001C
through
0x4040-005C
— Reserved
0x4040-0060 SADIV
Audio clock divider register. See Section 14.4, “Serial Audio Clocks
and Sampling Frequencies”.
0x4040-0064
through
0x4040-007C
— Reserved
0x4040-0080 SADR Serial Audio Data Register (TX and RX FIFO access register).