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Intel® PXA26x Processor Family Developer’s Manual xiii
Contents
17.5.4 Interrupt Enable Register (IER) ........................................................................17-13
17.5.5 Interrupt Identification Register (IIR).................................................................17-14
17.5.6 FIFO Control Register (FCR)............................................................................17-17
17.5.7 Receive FIFO Occupancy Register (FOR) .......................................................17-18
17.5.8 Auto-Baud Control Register (ABR) ...................................................................17-19
17.5.9 Auto-Baud Count Register (ACR).....................................................................17-20
17.5.10 Line Control Register (LCR)..............................................................................17-21
17.5.11 Line Status Register (LSR) ...............................................................................17-23
17.5.12 Modem Control Register (MCR) .......................................................................17-26
17.5.13 Modem Status Register (MSR).........................................................................17-28
17.5.14 Scratchpad Register (SPR) ..............................................................................17-29
17.5.15 Infrared Selection Register (ISR)......................................................................17-30
17.6 Hardware UART Register Summary..............................................................................17-31
18 Internal Flash..............................................................................................................................18-1
18.1 Initialization ......................................................................................................................18-1
18.1.1 Intel StrataFlash® Memory Reset Configuration ................................................18-1
18.1.2 BOOT_SEL[2:0] Configuration ...........................................................................18-2
18.1.3 Determining the Size and Configuration of Flash Using Software......................18-2
18.1.4 SXCNFG Configuration ......................................................................................18-2
18.1.5 Configuring the Intel StrataFlash® Memory........................................................18-3
18.2 Additional Intel StrataFlash® Memory Information ..........................................................18-6
Figures
2-1 Block Diagram ...........................................................................................................................2-2
2-2 Memory Map (Part One) — From 0x8000 0000 to 0xFFFF FFFF...........................................2-34
2-3 Memory Map (Part Two) — From 0x0000 0000 to 0x7FFF FFFF...........................................2-35
3-1 Clocks Manager Block Diagram ................................................................................................3-3
4-1 General-Purpose I/O Block Diagram .........................................................................................4-2
4-2 Interrupt Controller Block Diagram ..........................................................................................4-24
4-3 PWMn Block Diagram..............................................................................................................4-43
4-4 Basic Pulse Width Waveform ..................................................................................................4-47
5-1 DMAC Block Diagram................................................................................................................5-2
5-2 DREQ timing requirements........................................................................................................5-3
5-3 No-Descriptor Fetch Mode Channel State.................................................................................5-7
5-4 Descriptor Fetch Mode Channel State.......................................................................................5-8
5-5 Little Endian Transfers.............................................................................................................5-10
6-1 General Memory Interface Configuration...................................................................................6-2
6-2 SDRAM Memory System Example............................................................................................6-5
6-3 Asynchronous Static Memory System Example........................................................................6-6
6-4 External to Internal Address Mapping Options ........................................................................6-19
6-5 SDRAM Read ..........................................................................................................................6-27
6-6 SDRAM Read With a Second Read to Same Bank, Same Row .............................................6-27
6-7 SDRAM Read With a Second Read to Same Bank, Different Row.........................................6-28
6-8 SDRAM Read With a Second Read to a Different Bank .........................................................6-28
6-9 SDRAM Write ..........................................................................................................................6-29
6-10 SDRAM Write With a Second Write to Same Bank, Same Row .............................................6-29
6-11 SMROM Read Timing Diagram Half-Memory Clock Frequency, ............................................6-38
6-12 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................6-40
6-13 MSC0/1/2 Register Bitmap ......................................................................................................6-44